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公开(公告)号：US20080176368A1
公开(公告)日：2008-07-24
申请号：US11841817
申请日：2007-08-20
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
摘要翻译： 半导体器件包括半导体衬底，形成在衬底上的nMISFET，nMISFET包括形成在衬底上的第一电介质和形成在第一电介质上的第一金属栅极，并由选自Ti，Zr，Hf， Ta，Sc，Y，镧系元素和锕系和选自所述一种金属元素的硼化物，硅化物和锗化合物的一种，以及形成在所述衬底上的pMISFET，所述pMISFET包括形成在所述衬底上的第二电介质和第二金属 栅电极形成在第二电介质上并由与第一金属栅电极相同的材料制成，第二电介质面向第二金属栅电极的至少一部分由绝缘材料制成，绝缘材料与至少一部分 的第一电介质面向第一金属栅电极。
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公开(公告)号：US20070145488A1
公开(公告)日：2007-06-28
申请号：US11461646
申请日：2006-08-01
IPC分类号： H01L29/94
CPC分类号： H01L21/823842 , H01L21/823835
摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on the substrate, the p-channel MIS transistor having a first gate electrode, and an n-channel MIS transistor formed on the substrate separately from the p-channel MIS transistor, the n-channel MIS transistor having a second gate electrode. Each of the first gate electrode and the second gate electrode is formed of an alloy of Ta and C in which a mole ratio of C to Ta (C/Ta) is from 2 to 4.
摘要翻译： 半导体器件包括衬底，形成在衬底上的p沟道MIS晶体管，具有第一栅电极的p沟道MIS晶体管和与p沟道MIS晶体管分开形成在衬底上的n沟道MIS晶体管， 该n沟道MIS晶体管具有第二栅电极。 第一栅极电极和第二栅极电极由Ta和C的合金形成，其中C与Ta（C / Ta）的摩尔比为2〜4。
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23.发明授权公开(公告)号：US08633526B2
公开(公告)日：2014-01-21
申请号：US13234657
申请日：2011-09-16
申请人： Shigeki Hattori , Reika Ichihara , Masaya Terai , Hideyuki Nishizawa , Tsukasa Tada , Koji Asakawa , Hiroyuki Fuke , Satoshi Mikoshiba , Yoshiaki Fukuzumi , Hideaki Aochi
发明人： Shigeki Hattori , Reika Ichihara , Masaya Terai , Hideyuki Nishizawa , Tsukasa Tada , Koji Asakawa , Hiroyuki Fuke , Satoshi Mikoshiba , Yoshiaki Fukuzumi , Hideaki Aochi
IPC分类号： H01L27/108
CPC分类号： H01L29/513 , H01L21/02118 , H01L21/02227 , H01L21/28282 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L51/0591
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a first stacked structure body, a first semiconductor layer, a first organic film, a first semiconductor-side insulating film, and a first electrode-side insulating film. The first stacked structure body includes a plurality of first electrode films stacked along a first direction and a first inter-electrode insulating film provided between the first electrode films. The first semiconductor layer is opposed to side faces of the first electrode films. The first organic film is provided between the side faces of the first electrode films and the first semiconductor layer and containing an organic compound. The first semiconductor-side insulating film is provided between the first organic film and the first semiconductor layer. The first electrode-side insulating film provided between the first organic film and the side faces of the first electrode films.
摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一层叠结构体，第一半导体层，第一有机膜，第一半导体侧绝缘膜和第一电极侧绝缘膜。 第一堆叠结构体包括沿着第一方向堆叠的多个第一电极膜和设置在第一电极膜之间的第一电极间绝缘膜。 第一半导体层与第一电极膜的侧面相对。 第一有机膜设置在第一电极膜和第一半导体层的侧面之间并含有有机化合物。 第一半导体侧绝缘膜设置在第一有机膜和第一半导体层之间。 设置在第一有机膜和第一电极膜的侧面之间的第一电极侧绝缘膜。
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公开(公告)号：US08456890B2
公开(公告)日：2013-06-04
申请号：US13053677
申请日：2011-03-22
申请人： Reika Ichihara
发明人： Reika Ichihara
IPC分类号： G11C11/00
CPC分类号： G11C11/5685 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0092 , G11C2211/562 , G11C2211/563 , G11C2213/76 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： According to one embodiment, a multi-level resistance change memory includes a memory cell includes first and second resistance change films connected in series, and a capacitor connected in parallel to the first resistance change film, a voltage pulse generating circuit generating a first voltage pulse with a first pulse width to divide a voltage of the first voltage pulse into the first and second resistance change films based on a resistance ratio thereof, and generating a second voltage pulse with a second pulse width shorter than the first pulse width to apply a voltage of the second voltage pulse to the second resistance change film by a transient response of the capacitor, and a control circuit which is stored multi-level data to the memory cell by using the first and second voltage pulses in a writing.
摘要翻译： 根据一个实施例，多电平电阻变化存储器包括存储单元，包括串联连接的第一和第二电阻变化膜以及并联连接到第一电阻变化膜的电容器，产生第一电压脉冲的电压脉冲发生电路 具有第一脉冲宽度，以基于其电阻比将第一电压脉冲的电压分成第一和第二电阻变化膜，并产生具有比第一脉冲宽度短的第二脉冲宽度的第二电压脉冲，以施加电压 通过电容器的瞬态响应将第二电压脉冲施加到第二电阻变化膜;以及控制电路，其通过在写入中使用第一和第二电压脉冲将多电平数据存储到存储单元。
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公开(公告)号：US20120211719A1
公开(公告)日：2012-08-23
申请号：US13228753
申请日：2011-09-09
申请人： Takashi HAIMOTO , Reika Ichihara , Haruka Kusai
发明人： Takashi HAIMOTO , Reika Ichihara , Haruka Kusai
IPC分类号： H01L45/00
CPC分类号： H01L45/085 , G11C11/5614 , G11C13/0011 , H01L27/2436 , H01L27/2463 , H01L45/1233 , H01L45/1266 , H01L45/148
摘要： According to one embodiment, a first electrode includes a metal element. A second electrode includes a semiconductor element. A third electrode includes a metal element. A first variable resistive layer is arranged between the first electrode and the second electrode and is capable of reversibly changing a resistance by filament formation and dissolution of the metal element of the first electrode. A second variable resistive layer is arranged between the second electrode and the third electrode and is capable of reversibly changing a resistance by filament formation and dissolution of the metal element of the third electrode.
摘要翻译： 根据一个实施例，第一电极包括金属元件。 第二电极包括半导体元件。 第三电极包括金属元件。 第一可变电阻层布置在第一电极和第二电极之间，并且能够通过灯丝形成和第一电极的金属元件的溶解来可逆地改变电阻。 第二可变电阻层布置在第二电极和第三电极之间，并且能够通过灯丝形成和第三电极的金属元件的溶解来可逆地改变电阻。
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公开(公告)号：US08053300B2
公开(公告)日：2011-11-08
申请号：US11841817
申请日：2007-08-20
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
摘要翻译： 半导体器件包括半导体衬底，形成在衬底上的nMISFET，nMISFET包括形成在衬底上的第一电介质和形成在第一电介质上的第一金属栅极，并由选自Ti，Zr，Hf， Ta，Sc，Y，镧系元素和锕系和选自所述一种金属元素的硼化物，硅化物和锗化合物的一种，以及形成在所述衬底上的pMISFET，所述pMISFET包括形成在所述衬底上的第二电介质和第二金属 栅电极形成在第二电介质上并由与第一金属栅电极相同的材料制成，第二电介质面向第二金属栅电极的至少一部分由绝缘材料制成，绝缘材料与至少一部分 的第一电介质面向第一金属栅电极。
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公开(公告)号：US20100171184A1
公开(公告)日：2010-07-08
申请号：US12654490
申请日：2009-12-22
IPC分类号： H01L27/092
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
摘要翻译： 半导体器件包括半导体衬底，形成在衬底上的nMISFET，nMISFET包括形成在衬底上的第一电介质和形成在第一电介质上的第一金属栅极，并由选自Ti，Zr，Hf， Ta，Sc，Y，镧系元素和锕系和选自所述一种金属元素的硼化物，硅化物和锗化合物的一种，以及形成在所述衬底上的pMISFET，所述pMISFET包括形成在所述衬底上的第二电介质和第二金属 栅电极形成在第二电介质上并由与第一金属栅电极相同的材料制成，第二电介质面向第二金属栅电极的至少一部分由绝缘材料制成，绝缘材料与至少一部分 的第一电介质面向第一金属栅电极。
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28.发明授权Method of making p-channel and n-channel MIS transistors using single film formation of TaC 有权使用TaC单膜形成制造p沟道和n沟道MIS晶体管的方法公开(公告)号：US07745888B2
公开(公告)日：2010-06-29
申请号：US12232078
申请日：2008-09-10
IPC分类号： H01L29/76
CPC分类号： H01L21/823842
摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.
摘要翻译： 半导体器件包括衬底，形成在衬底上的n型阱上的p沟道MIS晶体管，具有形成在其上并由Ta-C合金形成的第一栅极电介质和第一栅电极，其中晶体取向比例 膜厚方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]的TaC（111）面为80％以上，n型沟道MIS晶体管形成在p- 在基板上良好地形成具有形成在其上的第二栅极电介质和第二栅电极，并且由TaC（111）在膜厚度方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]为60％以下。
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公开(公告)号：US07718521B2
公开(公告)日：2010-05-18
申请号：US12133605
申请日：2008-06-05
IPC分类号： H01L21/3205
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28088 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate insulating layer formed on the P-type semiconductor layer, and a second gate electrode formed on the second gate insulating layer.
摘要翻译： 公开了一种包括P沟道MIS晶体管的半导体器件，其包括N型半导体层，形成在N型半导体层上并含有金属的碳化合物的第一栅极绝缘层和N沟道MIS 晶体管，其包括P型半导体层，形成在P型半导体层上的第二栅极绝缘层和形成在第二栅极绝缘层上的第二栅电极。
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公开(公告)号：US20090267159A1
公开(公告)日：2009-10-29
申请号：US12388965
申请日：2009-02-19
申请人： Kosuke Tstsumura , Masakazu Goto , Reika Ichihara , Masato Koyama , Shigeru Kawanaka , Kazuaki Nakajima
发明人： Kosuke Tstsumura , Masakazu Goto , Reika Ichihara , Masato Koyama , Shigeru Kawanaka , Kazuaki Nakajima
IPC分类号： H01L27/092
CPC分类号： H01L21/823828 , H01L21/823842 , H01L29/785
摘要： A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate dielectric formed on the substrate and a first gate electrode layer formed on the first dielectric, and an n-channel MIS transistor formed on the substrate, the n-channel transistor having a second gate dielectric formed on the substrate and a second gate electrode layer formed on the second dielectric. A bottom layer of the first gate electrode layer in contact with the first gate dielectric and a bottom layer of the second gate electrode layer in contact with the second gate dielectric have the same orientation and the same composition including Ta and C, and a mole ratio of Ta to a total of C and Ta, (Ta/(Ta+C)), is larger than 0.5.
摘要翻译： 半导体器件包括半导体衬底，形成在衬底上的p沟道MIS晶体管，形成在衬底上的第一栅极电介质的p沟道晶体管和形成在第一电介质上的第一栅极电极层，以及n沟道 形成在衬底上的MIS晶体管，所述n沟道晶体管具有形成在衬底上的第二栅极电介质和形成在第二电介质上的第二栅极电极层。 与第一栅极电介质接触的第一栅极电极层的底层和与第二栅极电介质接触的第二栅电极层的底层具有相同的取向和相同的组成，包括Ta和C，以及摩尔比 的Ta与总计C和Ta（Ta /（Ta + C））大于0.5。
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