Soft error immune CMOS static RAM cell
    23.
    发明授权
    Soft error immune CMOS static RAM cell 失效
    软错误免疫CMOS静态RAM单元

    公开(公告)号:US5338963A

    公开(公告)日:1994-08-16

    申请号:US43090

    申请日:1993-04-05

    CPC分类号: H01L27/1104 Y10S257/903

    摘要: Soft error immunity of a storage cell is greatly increased by division of a storage node into at least two portions and location of those portions on opposite sides of an isolation structure, such as a well of a conductivity type opposite to that of the substrate in which transistors of the memory cell may also be formed. The isolation structure thus limits collection of charge to only one of the portions of the storage node and reduces charge collection efficiency to a level where a critical amount of charge cannot be collected in all but a statistically negligible number of cases when such charge is engendered by impingement by ionizing radiation, such as energetic alpha particles. The layout of the memory cell having this feature also advantageously provides a simplified topology for the formation of additional ports comprising word line access transistors and bit lines.

    摘要翻译: 通过将存储节点划分成隔离结构的相对侧上的这些部分的至少两个部分和位置,例如与基板的导电类型相反的阱的阱的位置,存储单元的软错误抗扰度大大增加,其中 还可以形成存储单元的晶体管。 因此,隔离结构将电荷收集限制在存储节点的仅一个部分,并且将电荷收集效率降低到在所有这些电荷不能被收集的情况下不能收集临界量的电荷的水平,但是当这种电荷由 通过电离辐射的冲击,例如能量α粒子。 具有该特征的存储单元的布局也有利地提供了用于形成包括字线访问晶体管和位线的附加端口的简化拓扑。