公开(公告)号：US11973010B2

公开(公告)日：2024-04-30

申请号：US17490038

申请日：2021-09-30

Applicant: Richtek Technology Corporation

Inventor： Hao-Lin Yen ,  Heng-Chi Huang ,  Yong-Zhong Hu

IPC: H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L23/49568 ,  H01L21/4825 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952

Abstract: A chip packaging method includes: providing a wafer, on which multiple bumps are formed; cutting the wafer into multiple chip units, wherein multiple vertical heat conduction elements are formed on the wafer or the chip units; disposing the chip units on a base material; and providing a package material to encapsulate lateral sides and a bottom surface of each of the chip units, to form a chip package unit, wherein the bottom surface of the chip unit faces the base material; wherein, in the chip package unit, the bumps on the chip units abut against the base material, and wherein the vertical heat conduction elements directly connect to the base material, or the base material includes multiple through-holes and the vertical heat conduction elements pass through the multiple through-holes in the base material.

公开(公告)号：US20220367309A1

公开(公告)日：2022-11-17

申请号：US17718125

申请日：2022-04-11

Applicant: Richtek Technology Corporation

Inventor： Hao-Lin Yen ,  Heng-Chi Huang ,  Yong-Zhong Hu

IPC: H01L23/34 ,  H01L23/31 ,  H01L21/56

Abstract: A chip package unit includes: a base material; at least one chip, disposed on the base material; a package material, enclosing the base material and the chip; and at least one heat dissipation paste curing layer, formed by curing the heat dissipation paste, on a top side of the package material or a back side of the chip in a printed pattern.

公开(公告)号：US11469162B2

公开(公告)日：2022-10-11

申请号：US17356810

申请日：2021-06-24

Applicant: Richtek Technology Corporation

Inventor： Hao-Lin Yen ,  Heng-Chi Huang ,  Yong-Zhong Hu

IPC: H01L23/495 ,  H01L23/34 ,  H01L23/28 ,  H01L21/00 ,  H05K7/20 ,  H01L23/31 ,  H01L25/07 ,  H01L23/14 ,  H01L25/075 ,  H01L23/00 ,  H01L23/40

Abstract: The present invention provides a chip packaging method, which includes: providing a base material, which includes plural finger contacts; disposing plural chips on the base material by flip chip mounting technology, and disposing plural vertical heat conducting elements surrounding each of the chips to connect the finger contacts on the base material; providing a packaging material to encapsulate the base material, the chips, and the vertical heat conducting elements; adhering a metal film on the packaging material via an adhesive layer, to form a package structure; and cutting the package structure into plural chip package units, wherein each of the chip package units includes one of the chips, a portion of the base material, a portion of the metal film, and a portion of the vertical heat conducting elements surrounding the chip.

公开(公告)号：US20220223464A1

公开(公告)日：2022-07-14

申请号：US17547829

申请日：2021-12-10

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kuo-Chin Chiu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.