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21.发明授权Method and apparatus for electronically aligning capacitively coupled chip pads 有权用于电子对准电容耦合芯片焊盘的方法和装置公开(公告)号：US06812046B2
公开(公告)日：2004-11-02
申请号：US10207671
申请日：2002-07-29
IPC分类号： H01L2166
CPC分类号： H04B5/0012 , G06F17/5077 , H01L23/48 , H01L23/544 , H01L2223/54473 , H01L2225/06531 , H01L2924/0002 , H01L2924/0001
摘要： One embodiment of the present invention provides a system that electronically aligns pads on different semiconductor chips to facilitate communication between the semiconductor chips through capacitive coupling. The system operates by measuring an alignment between a first chip and a second chip, wherein the first chip is situated face-to-face with the second chip so that transmitter pads on the first chip are capacitively coupled with receiver pads on the second chip. Next, the system uses the measured alignment to associate transmitter pads on the first chip with proximate receiver pads on the second chip. The system then selectively routes data signals to transmitter pads on the first chip so that the data signals are communicated through capacitive coupling to intended receiver pads in the second chip that are proximate to the transmitter pads.
摘要翻译： 本发明的一个实施例提供一种系统，其电子地对准不同半导体芯片上的焊盘，以便于通过电容耦合在半导体芯片之间进行通信。 该系统通过测量第一芯片和第二芯片之间的对准来工作，其中第一芯片与第二芯片面对面设置，使得第一芯片上的发射器焊盘与第二芯片上的接收器焊盘电容耦合。 接下来，系统使用测量的对准来将第一芯片上的发射器焊盘与第二芯片上的接近焊盘相关联。 然后，系统选择性地将数据信号路由到第一芯片上的发射机焊盘，使得数据信号通过电容耦合传递到靠近发射器焊盘的第二芯片中的预期接收器焊盘。
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公开(公告)号：US5943491A
公开(公告)日：1999-08-24
申请号：US954251
申请日：1997-10-20
CPC分类号： G06F9/3869
摘要： In certain systems where a series of stages are employed, it is desirable to control the action of a stage without possibility of interference form adjacent stages. A circuit of linked mutual exclusion elements is described which renders inactive the stages adjacent to an active stage, or inhibits action in a stage if any of its neighbors is active. This ensures that the stages adjacent to an active stage remain inactive, thereby avoiding problems associated with input events changing while an adjacent stage is active.
摘要翻译： 在采用一系列级的某些系统中，期望控制一个阶段的动作，而不会产生相邻阶段的干扰。 描述了链接的互斥元件的电路，其使与活动阶段相邻的阶段不活动，或者如果其邻居中的任何一个活动的话，在一个阶段中禁止动作。 这确保与活动阶段相邻的阶段保持不活动，从而避免与相邻阶段有效时改变输入事件相关的问题。
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公开(公告)号：US06741616B1
公开(公告)日：2004-05-25
申请号：US09685009
申请日：2000-10-05
IPC分类号： H04J304
CPC分类号： H04L12/4625 , H04L49/101
摘要： One embodiment of the present invention provides a system that facilitates asynchronously routing data within a circuit. This system includes a data destination horn, for routing data from a trunk line to a plurality of destinations. This data destination horn includes a plurality of one-to-many switching elements organized into a tree of at least one level that fans out from the trunk line to the plurality of destinations. It also includes a plurality of memory elements for storing data in transit between the plurality of one-to-many switching elements. An asynchronous control structure is coupled to the data destination horn, and is configured to control the propagation of data through the data destination horn, so that when a given data item appears at an input of a memory element, the given data item is asynchronously latched into the memory element as soon space becomes available in the memory element without having to wait for a clock signal. One embodiment of the present invention additionally includes a data source funnel, for routing data from a plurality of sources into the trunk line. This data source funnel includes a plurality of many-to-one switching elements organized into a tree of at least one level that fans in from the plurality of sources to into the trunk line. It also includes a plurality of funnel memory elements for storing data in transit between the plurality of many-to-one switching elements. Moreover, the asynchronous control structure is additionally configured to control propagation of data through the data source funnel.
摘要翻译： 本发明的一个实施例提供一种便于在电路内异步路由数据的系统。 该系统包括数据目的地喇叭，用于将数据从中继线路由到多个目的地。 该数据目的地喇叭包括组合成至少一个级别的树的多个一对多交换元件，其从干线到多个目的地扇出。 它还包括用于存储在多个一对多交换元件之间传输的数据的多个存储元件。 异步控制结构被耦合到数据目标喇叭，并且被配置为控制数据通过数据目的地喇叭的传播，使得当给定的数据项出现在存储器元件的输入端时，给定的数据项被异步锁存 随着空间在存储器元件中可用，而不必等待时钟信号，就进入存储元件。 本发明的一个实施例还包括数据源漏斗，用于将数据从多个源路由到干线。 该数据源漏斗包括多个多对一的开关元件，其组织成至少一个级别的树，该多个级别的风扇从多个源中进入干线。 它还包括多个漏斗存储器元件，用于存储在多个多对一开关元件之间的传输中的数据。 此外，异步控制结构还被配置为控制数据通过数据源漏斗的传播。
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24.发明授权Method and modules for control of pipelines carrying data using pipelines carrying control signals 失效使用承载控制信号的管道控制承载数据的管道的方法和模块公开(公告)号：US06360288B1
公开(公告)日：2002-03-19
申请号：US08953767
申请日：1997-10-17
IPC分类号： G06F1300
CPC分类号： G06F9/3869 , G06F9/3867
摘要： A computer system is described in which control of the flow of data items in one pipeline is achieved using the values of control elements in another pipeline. Typically, each pipeline includes elements known as “places” and “paths,” and the pipelines have special connections between them by which the data present in a place in a first pipeline can be used to control the disposition of data in the second pipeline. For example, the first pipeline can control the second pipeline to enable the addition, deletion, or steering of data items in the second pipeline.
摘要翻译： 描述了一种计算机系统，其中使用另一流水线中的控制元件的值来实现一条流水线中的数据项流的控制。 通常，每个管道包括被称为“地点”和“路径”的元件，并且管道在它们之间具有特殊的连接，通过该特殊连接，可以使用存在于第一管道中的位置的数据来控制第二管道中的数据的布置。 例如，第一流水线可以控制第二流水线，以允许第二流水线中的数据项的添加，删除或转向。
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公开(公告)号：US6085316A
公开(公告)日：2000-07-04
申请号：US123587
申请日：1998-07-28
申请人： Ivan E. Sutherland , Charles E. Molnar, deceased , Ian W. Jones , William S. Coates , Jon Lexau
发明人： Ivan E. Sutherland , Charles E. Molnar, deceased , Ian W. Jones , William S. Coates , Jon Lexau
CPC分类号： G06F9/3873 , G06F15/8007 , G06F15/8053 , G06F9/3867
摘要： A layered counterflow pipeline structure is described in which sub-tasks performed at each stage in a counterflow pipeline processor are separated into different layers. As words flow through the counterflow pipeline processor, they are divided into partial words which are supplied to the different layers, GET, CHECK and PROCESS, for appropriate handling by that portion of each stage. In the GET layer, partial words passing through each stage are analyzed to determine whether they constitute an encounter pair. In the CHECK layer a determination is made as to whether the word selected by the GET layer requires further modification. Finally, in the PROCESS layer operations are performed on the words themselves based upon control messages from the other layers. The layers of the processor communicate with each other using suitable communication paths such as First In First Out registers.
摘要翻译： 描述了分层逆流管线结构，其中在逆流管线处理器中的每个阶段执行的子任务被分成不同的层。 当文字流过逆流流水线处理器时，它们被分成供应给不同层的部分单词，GET，CHECK和PROCESS，以便每个阶段的该部分进行适当的处理。 在GET层中，分析通过每个阶段的部分单词，以确定它们是否构成遇到对。 在CHECK层中，确定由GET层选择的单词是否需要进一步修改。 最后，在PROCESS层中，基于来自其他层的控制消息对单词本身执行操作。 处理器的层使用诸如先进先出寄存器之类的合适的通信路径彼此通信。
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公开(公告)号：US5955898A
公开(公告)日：1999-09-21
申请号：US885169
申请日：1997-06-30
IPC分类号： H03K17/693 , H03K19/0948
CPC分类号： H03K17/693
摘要： A logic gate includes a plurality of pass gates forming a double rail pass gate XOR or reversing switch providing the same functionality as a conventional XOR gate. Consequently, the pass gate XOR can substitute for XOR gates in circuits such as a selector circuit and decision wait circuit, but with faster responses and fewer transistors than the conventional XOR gate. Each pass gate includes a P-type and an N-type transistor coupled in parallel. A control input and its complement are coupled to the gates of the transistors to selectively pass signals at the input of the pass gate to its output.
摘要翻译： 逻辑门包括形成双轨栅极XOR或反向开关的多个栅极，提供与传统XOR栅极相同的功能。 因此，通过门XOR可以在诸如选择器电路和判决等待电路的电路中替代XOR门，但是具有比常规XOR门更快的响应和更少的晶体管。 每个通过门包括并联耦合的P型和N型晶体管。 控制输入及其补码耦合到晶体管的栅极，以选择性地将通孔的输入端处的信号传递到其输出端。
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27.发明授权公开(公告)号：US06707317B2
公开(公告)日：2004-03-16
申请号：US10135166
申请日：2002-04-29
IPC分类号： H03K19096
CPC分类号： H03K19/0966
摘要： One embodiment of the present invention provides a domino logic circuit that operates asynchronously. This domino logic circuit includes a number of stages, including a present stage that receives one or more inputs from a prior stage and generates one or more outputs for a next stage. It also includes a control circuit that ensures that the present stage enters a precharging state before entering a subsequent evaluation state in which one or more inputs of the present stage are used to generate one or more outputs. This control circuit receives a prior control signal from the prior stage and sends a present control signal to the next stage
摘要翻译： 本发明的一个实施例提供了一种异步操作的多米诺逻辑电路。 该多米诺骨牌逻辑电路包括多个级，包括从现有级接收一个或多个输入并为下一级生成一个或多个输出的当前级。 它还包括控制电路，其确保当前级在进入后级评估状态之前进入预充电状态，其中使用当前级的一个或多个输入来产生一个或多个输出。 该控制电路接收来自前一级的先前控制信号，并将当前控制信号发送到下一级
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公开(公告)号：US6072805A
公开(公告)日：2000-06-06
申请号：US884927
申请日：1997-06-30
IPC分类号： H04J3/02
CPC分类号： G06F13/364
摘要： An arbiter is disclosed for determining a sequence of signals indicative of events occurring variously on at least two input connections. The arbiter includes a first input connection and a second input connection for carrying the signals indicative of events. A first input queue for storing representations of events that are waiting to be processed is connected to the first input connection, and a second input queue also for storing representations of events that are waiting to be processed is connected to the second input connection. An arbitration circuit coupled to the first input queue and to the second input queue receives the representations of events from each of the queues and determines the temporal order of occurrence of the event representations in the queues when the events arrive at time intervals greater than a specified amount, and arbitrarily assigns a sequence to one or the other of the events from the queues when the events arrive at time intervals equal to or less than the specified amount. In response the arbitration circuit reports the temporal order or arbitrary sequence as a sequence of output signals and removes each event representation from the appropriate queue when reporting its temporal order or sequence.
摘要翻译： 公开了一种用于确定指示在至少两个输入连接上不同地发生的事件的信号序列的仲裁器。 仲裁器包括用于承载指示事件的信号的第一输入连接和第二输入连接。 用于存储等待被处理的事件的表示的第一输入队列连接到第一输入连接，并且还用于存储等待被处理的事件的表示的第二输入队列连接到第二输入连接。 耦合到第一输入队列和第二输入队列的仲裁电路从每个队列接收事件的表示，并且当事件以大于指定的时间间隔的时间间隔到达时，确定队列中的事件表示的出现的时间顺序 量，并且当事件以等于或小于指定量的时间间隔到达时，将序列任意地分配给队列中的一个或另一个事件。 作为响应，仲裁电路将时间顺序或任意序列报告为输出信号的序列，并在报告其时间顺序或序列时从适当的队列中移除每个事件表示。
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公开(公告)号：US5861762A
公开(公告)日：1999-01-19
申请号：US813054
申请日：1997-03-07
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： H03K19/21 , H03K19/0948
CPC分类号： H03K19/215
摘要： A four transistor XOR or XNOR gate includes an inverting stage and a non-inverting stage. The transistors in each stage are coupled so as to enable changing inputs and existing inputs to drive the output in the same direction. The XOR gate and XNOR gate take advantage of a known order or inputs to reduce the delay of the gate.
摘要翻译： 四极晶体管XOR或XNOR门包括反相级和非反相级。 每个级中的晶体管被耦合，以便能够改变输入和现有输入以在相同方向上驱动输出。 XOR门和XNOR门利用已知的顺序或输入来减少门的延迟。
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公开(公告)号：US4679213A
公开(公告)日：1987-07-07
申请号：US689635
申请日：1985-01-08
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
CPC分类号： G11C19/00
摘要： A queue form of asynchronous register is disclosed with signal paths commonly carrying elements of both data and control. Binaries are intercoupled in two sequences and are individually cross coupled to register "one" bits in one sequence and "zero" bits in the other. Bits are manifest by signal level changes. Individual binaries are driven by logic to accomplish an operational rule based on the states of neighboring binaries in both sequences. Each binary in each sequence is controlled by the states of the predecessor and successor in its sequence and the predecessor and successor of its associated binary in the other sequence. Specifically, if predecessor and successor binaries in a sequence are in different states, and predecessor and successor binaries of an associated binary in the other sequence are in the same state, the state of the predecessor is to be taken.
摘要翻译： 披露了具有通常携带数据和控制元素的信号路径的异步寄存器的队列形式。 二进制序列以两个序列相互配合，并且被单独交叉耦合以在一个序列中寄存“一个”比特，而在另一个序列中“零”比特。 位由信号电平变化表现。 单个二进制文件由逻辑驱动，以基于两个序列中的相邻二进制文件的状态来完成操作规则。 每个序列中的每个二进制由其序列中的前导和后继的状态以及在其他序列中的相关二进制的前导和后继来控制。 具体来说，如果序列中的前导和后继二进制文件处于不同的状态，并且其他序列中相关联的二进制文件的前导和后继二进制文件处于相同的状态，则将采用前导的状态。
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