公开(公告)号：US07321979B2

公开(公告)日：2008-01-22

申请号：US10763077

申请日：2004-01-22

申请人： Van Hoa Lee

发明人： Van Hoa Lee

IPC分类号： G06F1/04

CPC分类号： G06F9/30101 ,  G06F1/3203 ,  G06F1/324 ,  Y02D10/126

摘要： A method, apparatus, and computer instructions for changing an operating frequency for a system core logic used to interface to memory in the multi-processor data processing system. A determination is made as to whether the operating frequency should be changed from a default frequency to another frequency. Slave processors are placed in the multi-processor data processing system into a non-transactional mode, in response to determining the operating frequency should be changed from the default operating frequency to the another operating frequency. When the slave processors are in the non-transactional mode, the operating frequency is changed in the system core logic to other operating frequency by the master processor.

摘要翻译： 一种用于改变用于与多处理器数据处理系统中的存储器接口的系统核心逻辑的操作频率的方法，装置和计算机指令。 确定工作频率是否应该从默认频率改变到另一个频率。 从处理器被放置在多处理器数据处理系统中，成为非事务模式，响应于确定工作频率应该从默认工作频率改变到另一个工作频率。 当从属处理器处于非事务模式时，主处理器将工作频率在系统核心逻辑中改变为其他工作频率。

公开(公告)号：US06865688B2

公开(公告)日：2005-03-08

申请号：US09998047

申请日：2001-11-29

申请人： George John Dawkins ,  Van Hoa Lee

发明人： George John Dawkins ,  Van Hoa Lee

IPC分类号： G06F9/48 ,  G06F11/00

CPC分类号： G06F9/4812

摘要： A logical partition management apparatus and method for handling system reset interrupts (SRIS) are provided. The apparatus and method provide a SRI handler in the hypervisor that is capable of handling SRIs which may occur at any time during the operation of the multiprocessor computing system. The apparatus and method allow a hypervisor call to be completed before an SRI is handled. In this way, the SRI does not cause a processor of the symmetric multiprocessor (SMP) system to indefinitely hold a lock on a system resource and thus, other processors are not starved due to an inability to access the system resource.

摘要翻译： 提供了一种用于处理系统复位中断（SRIS）的逻辑分区管理装置和方法。 该装置和方法在管理程序中提供能够处理在多处理器计算系统的操作期间的任何时间可能发生的SRI的SRI处理程序。 该装置和方法允许在处理SRI之前完成管理程序调用。 以这种方式，SRI不会导致对称多处理器（SMP）系统的处理器无限期地保持对系统资源的锁定，因此，由于无法访问系统资源，其他处理器不会被饿死。

公开(公告)号：US06845470B2

公开(公告)日：2005-01-18

申请号：US10087920

申请日：2002-02-27

申请人： Christopher Harry Austen ,  Van Hoa Lee ,  Milton Devon Miller, II ,  Douglas Wayne Oliver

发明人： Christopher Harry Austen ,  Van Hoa Lee ,  Milton Devon Miller, II ,  Douglas Wayne Oliver

IPC分类号： G06F11/00 ,  G06F11/07

CPC分类号： G06F11/079 ,  G06F11/0712 ,  G06F11/0724 ,  G06F11/073

摘要： A method and system for identifying a source of a corrupt data in a memory in a multiprocessor computer system. When a computer program stores corrupt data causing a program failure or a system crash, the corrupt data and its address are identified. The multiprocessor computer system is shut down, and the corrupt data is cleared from the memory. Before fully re-booting the multiprocessor computer system, a processor is selected from the multiprocessor computer system to load and run monitor code designed to monitor the location where the corrupt data was stored. The program that previously stored the corrupt data is restarted, and the selected processor detects any re-storage of the corrupt data in the same memory address. All processors in the computer system are then immediately suspended. The registers of all processors suspected of storing corrupt data are inspected to determine the source of the corrupt data.

摘要翻译： 一种用于识别多处理器计算机系统中的存储器中的损坏数据的源的方法和系统。 当计算机程序存储导致程序故障或系统崩溃的损坏数据时，会识别损坏的数据及其地址。 多处理器计算机系统关闭，损坏的数据从存储器中清除。 在完全重新启动多处理器计算机系统之前，从多处理器计算机系统中选择一个处理器来加载和运行监视代码，该代码用于监视存储损坏数据的位置。 先前存储损坏数据的程序重新启动，所选择的处理器检测到同一存储器地址中的损坏数据的任何重新存储。 计算机系统中的所有处理器都将立即暂停。 检查怀疑存储损坏数据的所有处理器的寄存器，以确定损坏数据的来源。

公开(公告)号：US06842857B2

公开(公告)日：2005-01-11

申请号：US09833337

申请日：2001-04-12

申请人： Van Hoa Lee ,  Kiet Anh Tran

发明人： Van Hoa Lee ,  Kiet Anh Tran

IPC分类号： G06F15/177 ,  G06F9/445 ,  G06F9/00 ,  G06F15/167

CPC分类号： G06F15/177 ,  G06F9/4405

摘要： A method, apparatus and program for booting a non-uniform-memory-access (NUMA) machine are provided. The invention comprises configuring a plurality of standalone, symmetrical multiprocessing (SMP) systems to operate within a NUMA system. A master processor is selected within each SMP; the other processors in the SMP are designated as NUMA slave processors. A NUMA master processor is then chosen from the SMP master processors; the other SMP master processors are designated as NUMA slave processors. A unique NUMA ID is assigned to each SMP that will be part of the NUMA system. The SMPs are then booted in NUMA mode in one-pass with memory coherency established right at the beginning of the execution of the system firmware.

摘要翻译： 提供了用于引导非均匀存储器访问（NUMA）机器的方法，装置和程序。 本发明包括配置多个独立的对称多处理（SMP）系统以在NUMA系统内操作。 在每个SMP内选择主处理器; SMP中的其他处理器被指定为NUMA从属处理器。 然后从SMP主处理器中选择一个NUMA主处理器; 其他SMP主处理器被指定为NUMA从属处理器。 将为作为NUMA系统一部分的每个SMP分配唯一的NUMA ID。 然后，SMP在NUMA模式下一次性启动，并在系统固件执行开始时建立内存一致性。

公开(公告)号：US06728864B2

公开(公告)日：2004-04-27

申请号：US09773192

申请日：2001-01-31

申请人： Van Hoa Lee ,  Kiet Anh Tran

发明人： Van Hoa Lee ,  Kiet Anh Tran

IPC分类号： G06F1576

CPC分类号： G06F9/30181

摘要： A method, system and program for architecturally identifying data processor implementations are provided. The invention comprises assigning a plurality of least significant bits in a processor's identification register to a unique value. This value can be assigned to these bits permanently during manufacture and is used to identify the bit specification for a specific processor implementation. The present invention can be generalized to include any processor architecture that comprises a plurality of instruction subsets for different bit specifications.

摘要翻译： 提供了用于架构地识别数据处理器实现的方法，系统和程序。 本发明包括将处理器的识别寄存器中的多个最低有效位分配给唯一值。 该值可以在制造期间永久分配给这些位，并用于识别特定处理器实现的位规范。 本发明可以被概括为包括用于不同比特规格的包括多个指令子集的任何处理器架构。

公开(公告)号：US06717594B1

公开(公告)日：2004-04-06

申请号：US09668549

申请日：2000-09-25

申请人： Tam D. Bui ,  George John Dawkins ,  Van Hoa Lee ,  Jayeshkumar M. Patel ,  Kiet Anh Tran

发明人： Tam D. Bui ,  George John Dawkins ,  Van Hoa Lee ,  Jayeshkumar M. Patel ,  Kiet Anh Tran

IPC分类号： G06T1500

CPC分类号： G09G5/00 ,  G06F9/4401 ,  G06F9/4411 ,  G09G2330/026 ,  H04L41/0853 ,  H04L41/22 ,  H04L43/00 ,  H04L43/045 ,  H04L43/065 ,  H04L43/12 ,  Y10S715/965

摘要： A data processing system and method are disclosed for displaying a graphical depiction of the system configuration of the data processing system. Execution of a boot process of the data processing system is started. Prior to a completion of the boot process, a configuration of the data processing system is determined by the system itself. A graphical depiction of the configuration is then generated. The graphical depiction is then graphically displayed utilizing a display screen which is included in the data processing system. The graphical depiction illustrates each device included in the system as well as how the devices are interconnected. Thereafter, the execution of the boot process is completed. The steps of determining a configuration, generating a graphical depiction, and graphically displaying the graphical depiction are completed prior to completing the booting the data processing system, and thus prior to an operating system being executed by the data processing system.

摘要翻译： 公开了一种用于显示数据处理系统的系统配置的图形描述的数据处理系统和方法。 开始执行数据处理系统的启动过程。 在完成引导过程之前，数据处理系统的配置由系统本身确定。 然后生成配置的图形描述。 然后使用包括在数据处理系统中的显示屏来图形地显示图形描绘。 图形描述说明了系统中包括的每个设备以及设备如何互连。 此后，引导过程的执行完成。 确定配置，生成图形描述和图形显示图形描绘的步骤在完成启动数据处理系统之前，并且因此在操作系统由数据处理系统执行之前完成。

公开(公告)号：US06526496B1

公开(公告)日：2003-02-25

申请号：US09422364

申请日：1999-10-21

申请人： Steven Paul Hartman ,  Van Hoa Lee ,  Milton Devon Miller, II

发明人： Steven Paul Hartman ,  Van Hoa Lee ,  Milton Devon Miller, II

IPC分类号： G06F1204

CPC分类号： G06F12/0879

摘要： A burst transfer alignment apparatus and method are provided. An interface between the word-aligned subsystem and the double-word-aligned system bus loads a predetermined invalid bit pattern on the system bus corresponding to the second word of the double-word access, in response to a misaligned read. When execution of the predetermined invalid pattern is attempted, an execution exception is thrown. In response the cache line containing the invalid pattern giving rise to the exception is invalidated at the address of the invalid instruction data. Returning from the exception to the address of the invalid pattern, the cache line is refetched. The refetch occurs on an even word boundary, and therefore the refetched cache line transfers properly because the even word address coincides with a double word boundary expected by the bus system.

摘要翻译： 提供了一种突发转移对准装置和方法。 字对齐子系统和双字对齐系统总线之间的接口响应于未对准读取，加载对应于双字访问的第二字的系统总线上的预定无效位模式。 当尝试执行预定的无效模式时，抛出执行异常。 作为响应，包含引起异常的无效模式的高速缓存行在无效指令数据的地址无效。 从异常返回到无效模式的地址，重新缓存高速缓存行。 重写在偶数字边界上发生，因此，重写的高速缓存行正确地传输，因为偶数字地址与总线系统预期的双字边界一致。

公开(公告)号：US06223309B1

公开(公告)日：2001-04-24

申请号：US09165958

申请日：1998-10-02

申请人： Robert Christopher Dixon ,  Van Hoa Lee ,  Thoi Nguyen

发明人： Robert Christopher Dixon ,  Van Hoa Lee ,  Thoi Nguyen

IPC分类号： G06F1100

CPC分类号： G06F11/2215 ,  G06F11/1048

摘要： An ECC verification circuit including a first biasing circuit that is configured to output a predetermined logical signal. The verification circuit further includes a switch connected between the first biasing circuit and a first data bit line of a memory data bus of a computer system. The memory data bus includes a plurality of data bit lines and a plurality of check bit lines and the computer system includes error correction circuitry that is coupled to the memory data bus. The verification circuit is configured to activate the switch during a verification cycle of the computer system. In this manner, the predetermined logical signal is applied to the first data bit line during the verification cycle. The verification circuit is designed to apply a test state to the data bit lines and check bits lines of the memory data bus. The test state applied to the check bits line varies from the check bit state that would be generated by the ECC unit of the computer system upon receiving the test state that is applied to the data bit lines.

摘要翻译： ECC验证电路，包括被配置为输出预定逻辑信号的第一偏置电路。 验证电路还包括连接在计算机系统的存储器数据总线的第一偏置电路和第一数据位线之间的开关。 存储器数据总线包括多个数据位线和多个校验位线，并且计算机系统包括耦合到存储器数据总线的纠错电路。 验证电路被配置为在计算机系统的验证周期期间激活交换机。 以这种方式，在验证周期期间将预定的逻辑信号施加到第一数据位线。 验证电路被设计为将测试状态应用于数据位线并检查存储器数据总线的位线。 应用于校验位线的测试状态随着计算机系统的ECC单元在接收到应用于数据位线的测试状态时将产生的校验位状态变化。

公开(公告)号：US5953243A

公开(公告)日：1999-09-14

申请号：US164131

申请日：1998-09-30

申请人： Louis Bennie Capps, Jr. ,  Robert Christopher Dixon ,  Van Hoa Lee ,  Thoi Nguyen

发明人： Louis Bennie Capps, Jr. ,  Robert Christopher Dixon ,  Van Hoa Lee ,  Thoi Nguyen

IPC分类号： G06F1/00 ,  G06F11/00 ,  G06F13/42 ,  G11C5/00 ,  G11C5/02

CPC分类号： G11C5/06 ,  G06F11/006 ,  G06F13/4239 ,  G11C5/04

摘要： A computer system includes a memory subsystem which has DIMM slots capable of receiving both DRAM and SDRAM memory module devices. A memory device detection methodology detects the presence of installed memory modules in the memory module slots, and signal levels on predetermined pins of the installed memory modules are processed to identify the specific type of memory module installed. The mode of an associated memory controller is set according to the type of module detected to be present, and the characteristics for the memory module are read.

摘要翻译： 计算机系统包括具有能够接收DRAM和SDRAM存储器模块设备的DIMM插槽的存储器子系统。 存储器件检测方法检测存储器模块插槽中存在的已安装的存储器模块，并且处理所安装的存储器模块的预定引脚上的信号电平以识别所安装的存储器模块的具体类型。 相关联的存储器控​​制器的模式根据检测到的模块的类型来设置，并且读取存储器模块的特性。

公开(公告)号：US5642506A

公开(公告)日：1997-06-24

申请号：US587259

申请日：1996-01-16

申请人： Van Hoa Lee

发明人： Van Hoa Lee

IPC分类号： G06F9/445

CPC分类号： G06F15/177 ,  G06F9/4405

摘要： An apparatus and method for booting a multiprocessor computer system including providing a first portion of boot code to multiple processors for execution, selecting a first processor, the selection based on which of the multiple processors first successfully executes the first portion of the boot code, providing a second portion of the boot code only to the first processor, and the first processor executing the second portion of the boot code to configure the multiprocessor system.

摘要翻译： 一种用于引导多处理器计算机系统的装置和方法，包括向多个处理器提供引导代码的第一部分用于执行，选择第一处理器，所述选择基于多个处理器中的哪一个首先成功地执行引导代码的第一部分，提供 引导代码的第二部分仅到第一处理器，并且第一处理器执行引导代码的第二部分以配置多处理器系统。