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21.发明授权Setting a reference voltage in a memory controller trained to a memory device 有权将存储器控制器中的参考电压设置为训练到存储器件公开(公告)号：US08902681B2
公开(公告)日：2014-12-02
申请号：US13472891
申请日：2012-05-16
CPC分类号： G11C29/02 , G06F1/3296 , G11C29/022 , G11C29/025 , G11C29/028 , G11C29/50008 , Y02D10/172
摘要： Systems and methods to set a voltage value associated with a memory controller coupled to a memory device are disclosed. A particular method includes comparing test data of a test path to functional data of a functional path. The functional data may be generated based on device data received at a memory controller from a memory device. The test data may be affected by a voltage value applied to a resistor arrangement in electronic communication with the test path. The voltage value may be applied to the resistor arrangement based on the comparison.
摘要翻译： 公开了设置与耦合到存储器件的存储器控制器相关联的电压值的系统和方法。 一种特定的方法包括将测试路径的测试数据与功能路径的功能数据进行比较。 功能数据可以基于从存储器设备在存储器控制器处接收的设备数据来生成。 测试数据可能受到施加到与测试路径电子通信的电阻器布置的电压值的影响。 基于比较可以将电压值施加到电阻装置。
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22.发明授权Modular heat sink decoupling capacitor array forming heat sink fins and power distribution interposer module 失效模块化散热器去耦电容阵列形成散热鳍片和功率分配插件模块公开(公告)号：US07235875B2
公开(公告)日：2007-06-26
申请号：US11008798
申请日：2004-12-09
申请人： Roger Allen Booth, Jr. , Matthew Stephen Doyle , Don Alan Gilliland , Brian Edward Gregg , Lynn Robert Landin , Thomas W. Liang , Ankur Kanu Patel , Dennis James Wurth
发明人： Roger Allen Booth, Jr. , Matthew Stephen Doyle , Don Alan Gilliland , Brian Edward Gregg , Lynn Robert Landin , Thomas W. Liang , Ankur Kanu Patel , Dennis James Wurth
CPC分类号： H05K1/0231 , H01L23/3672 , H01L23/50 , H01L2924/0002 , H05K1/0203 , H05K3/301 , H05K2201/10454 , H05K2201/2018 , H01L2924/00
摘要： A modular heat sink decoupling capacitor array includes a plurality of modules, each defining parallel distributed decoupling plates, and each module forming a heat sink fi. Each module includes multiple spaced apart contacts for providing low inductance connections with an associated device. A power distribution interposer module is attached to a heat sink surface of the modular decoupling capacitor. The interposer module is used for implementing power delivery without using valuable ball grid array (BGA) connections and printed circuit board (PCB) layers.
摘要翻译： 模块化散热器去耦电容器阵列包括多个模块，每个模块限定平行分布式去耦板，并且每个模块形成散热片fi。 每个模块包括多个间隔开的触点，用于与相关联的装置提供低电感连接。 功率分配插入器模块连接到模块化去耦电容器的散热器表面。 内插器模块用于实现功率输送，而不使用有价值的球栅阵列（BGA）连接和印刷电路板（PCB）层。
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23.发明授权Training a memory controller and a memory device using multiple read and write operations 失效训练使用多个读写操作的存储器控制器和存储器件公开(公告)号：US08681571B2
公开(公告)日：2014-03-25
申请号：US12815844
申请日：2010-06-15
IPC分类号： G11C7/00
CPC分类号： H03K19/017545 , G06F13/1694 , G06F13/4072 , G11C7/1057 , G11C7/1084 , G11C29/022 , G11C29/025 , G11C29/028
摘要： Systems and methods to set a voltage value associated with a communication bus that includes memory controller coupled to a memory device are disclosed. A particular method may include performing a first calibration operation associated with first data written from a memory controller to a memory device. A second calibration operation may be associated with second data read at the memory controller from the memory device. The operating parameter may be set based on a result of at least one of the first and the second calibration operations at the memory device or the memory controller.
摘要翻译： 公开了设置与包括耦合到存储器件的存储器控制器的通信总线相关联的电压值的系统和方法。 特定方法可以包括执行与从存储器控制器写入存储器件的第一数据相关联的第一校准操作。 第二校准操作可以与存储器设备在存储器控制器处读取的第二数据相关联。 可以基于存储器装置或存储器控制器中的第一和第二校准操作中的至少一个的结果来设置操作参数。
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24.发明授权Setting a reference voltage in a memory controller trained to a memory device 有权将存储器控制器中的参考电压设置为训练到存储器件公开(公告)号：US08289784B2
公开(公告)日：2012-10-16
申请号：US12815739
申请日：2010-06-15
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G06F1/3296 , G11C29/022 , G11C29/025 , G11C29/028 , G11C29/50008 , Y02D10/172
摘要： Systems and methods to set a voltage value associated with a memory controller coupled to a memory device are disclosed. A particular method includes comparing test data of a test path to functional data of a functional path. The functional data may be generated based on device data received at a memory controller from a memory device. The test data may be affected by a voltage value applied to a resistor arrangement in electronic communication with the test path. The voltage value may be applied to the resistor arrangement based on the comparison.
摘要翻译： 公开了设置与耦合到存储器件的存储器控制器相关联的电压值的系统和方法。 一种特定的方法包括将测试路径的测试数据与功能路径的功能数据进行比较。 功能数据可以基于从存储器设备在存储器控制器处接收的设备数据来生成。 测试数据可能受到施加到与测试路径电子通信的电阻器布置的电压值的影响。 基于比较可以将电压值施加到电阻装置。
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25.发明申请Setting Controller Termination in a Memory Controller and Memory Device Interface in a Communication Bus 失效在通信总线中的存储器控制器和存储器件接口中设置控制器端接公开(公告)号：US20100192000A1
公开(公告)日：2010-07-29
申请号：US12361836
申请日：2009-01-29
CPC分类号： G06F13/4086
摘要： A DRAM and memory controller are coupled during driver training to reduce mismatches. The impedances of the system are controlled through a termination at the controller to yield improvements in timing margins. The coupling of the components on a shared electrical bus through adjustment of the termination values during training removes known offset issues.
摘要翻译： 在驱动程序训练期间，DRAM和存储器控制器耦合以减少错配。 通过控制器的终止来控制系统的阻抗，从而提高定时裕度。 通过在训练期间调整终端值，共享电气总线上的组件耦合可以消除已知的偏移问题。
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26.发明申请Method, Apparatus, and Computer Program Product for Implementing Optimized Channel Routing With Generation of FIR Coefficients 审中-公开用于实现FIR系数生成的优化信道路由的方法，装置和计算机程序产品公开(公告)号：US20080270100A1
公开(公告)日：2008-10-30
申请号：US11741261
申请日：2007-04-27
CPC分类号： G06F17/5077
摘要： A method, apparatus and computer program product implement optimized channel routing in an electronic package design. Electronic package physical design data are received. A physical design including a netlist including a plurality of nets is generated. Finite impulse response (FIR) driver coefficients are determined for each net in the netlist from simulation with generation of impulse responses of the netlist.
摘要翻译： 一种方法，装置和计算机程序产品在电子封装设计中实现优化的信道路由。 接收电子封装物理设计数据。 生成包括多个网的网表的物理设计。 通过网表的脉冲响应的产生，从网表中的每个网络确定有限冲激响应（FIR）驱动器系数。
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公开(公告)号：US20080205570A1
公开(公告)日：2008-08-28
申请号：US11678256
申请日：2007-02-23
申请人： Steven J. Baumgartner , Timothy C. Buchholtz , Andrew D. Davies , Thomas W. Liang , Andrew B. Maki , Thomas Pham , Dana M. Woeste , Daniel G. Young
发明人： Steven J. Baumgartner , Timothy C. Buchholtz , Andrew D. Davies , Thomas W. Liang , Andrew B. Maki , Thomas Pham , Dana M. Woeste , Daniel G. Young
IPC分类号： H03D3/24
CPC分类号： H03L7/0812 , H04L7/0008
摘要： A phase locked loop generates an output corresponding to a source synchronous input and an input link clock signal. A phase locking feedback system receives the input and an input link clock signal and detects phase deviations between the output and the input. The phase locking feedback system also adjusts an adjusted clock signal based on the phase deviations thereby causing the phase locking feedback system to generate the output so that the output has a steady phase relationship with the input. A first mechanism causes the phase locking feedback system not to track phase deviations between the output and the input upon occurrence of a first predefined event, thereby maintaining the adjusted clock signal at a current state.
摘要翻译： 锁相环产生对应于源同步输入和输入链路时钟信号的输出。 相位锁定反馈系统接收输入和输入链路时钟信号，并检测输出和输入之间的相位偏差。 相位锁定反馈系统还基于相位偏差来调整调整的时钟信号，从而使相位锁定反馈系统产生输出，使得输出与输入具有稳定的相位关系。 第一机制使得相位锁定反馈系统在出现第一预定义事件时不跟踪输出和输入之间的相位偏差，从而将经调整的时钟信号保持在当前状态。
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