公开(公告)号：US08743516B2

公开(公告)日：2014-06-03

申请号：US13451312

申请日：2012-04-19

申请人： Chai Ean Gill ,  Rouying Zhan

发明人： Chai Ean Gill ,  Rouying Zhan

IPC分类号： H02H9/00 ,  H02H9/04 ,  H01L27/02

CPC分类号： H01L27/0259 ,  H02H9/041

摘要： An area-efficient, high voltage, dual polarity ESD protection device (200) is provided for protecting multiple pins (30, 40) against ESD events by using a plurality of stacked NPN devices (38, 48, 39) which have separately controllable breakdown voltages and which share one or common NPN devices (39), thereby reducing the footprint of the high voltage ESD protection circuits without reducing robustness and functionality.

摘要翻译： 提供了一种区域高效，高电压，双极性ESD保护装置（200），用于通过使用多个堆叠的NPN装置（38,48,39）来保护多个针脚（30,40）免受ESD事件的影响，这些NPN装置具有分别可控的击穿 电压并且共享一个或公共NPN器件（39），从而减少高压ESD保护电路的覆盖，而不降低鲁棒性和功能性。

公开(公告)号：US20130157433A1

公开(公告)日：2013-06-20

申请号：US13770548

申请日：2013-02-19

申请人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

发明人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

IPC分类号： H01L29/66

CPC分类号： H01L21/8228 ,  H01L27/0259 ,  H01L29/66234

摘要： Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt1 of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 1

摘要翻译： 提供了形成静电放电保护（ESD）夹具的方法。 在一个实施例中，该方法包括形成至少一个具有延伸到衬底中的第一导电类型的第一阱区的晶体管。 至少一个晶体管形成有具有第二相反导电类型的另一阱区，其延伸到衬底中以部分地形成集电极。 晶体管阱区的横向边缘被隔开距离D，距离D至少部分地确定ESD钳位的阈值电压Vt1。 第一导电类型的基极接触形成在第一阱区中，并且与第二导电类型的发射极分开横向距离Lbe。 选择第一掺杂密度和横向距离Lbe以在1

公开(公告)号：US08455306B2

公开(公告)日：2013-06-04

申请号：US13480924

申请日：2012-05-25

申请人： Amaury Gendron ,  Chai Ean Gill ,  Rouying Zhan

发明人： Amaury Gendron ,  Chai Ean Gill ,  Rouying Zhan

IPC分类号： H01L21/332 ,  H01L21/00 ,  H01L27/02

CPC分类号： H01L21/00 ,  H01L27/0259 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/66121 ,  H01L29/87

摘要： Embodiments include methods for forming an electrostatic discharge (ESD) protection device coupled across input-output (I/O) and common terminals of a core circuit, where the ESD protection device includes first and second merged bipolar transistors. A base of the first transistor serves as collector of the second transistor and the base of the second transistor serves as collector of the first transistor, the bases having, respectively, first and second widths. A first resistance is coupled between an emitter and base of the first transistor and a second resistance is coupled between an emitter and base of the second transistor. ESD trigger voltage Vt1 and holding voltage Vh can be independently optimized by choosing appropriate base widths and resistances. By increasing Vh to approximately equal Vt1, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage.

摘要翻译： 实施例包括用于形成耦合在输入输出（I / O）和核心电路的公共端子之间的静电放电（ESD）保护装置的方法，其中ESD保护装置包括第一和第二合并双极晶体管。 第一晶体管的基极用作第二晶体管的集电极，第二晶体管的基极用作第一晶体管的集电极，基极分别具有第一和第二宽度。 第一电阻耦合在第一晶体管的发射极和基极之间，第二电阻耦合在第二晶体管的发射极和基极之间。 ESD触发电压Vt1和保持电压Vh可以通过选择合适的基极宽度和电阻来独立优化。 通过将Vh增加到大致相等的Vt1，ESD保护更稳健，特别是对于具有窄设计窗口的应用，例如，工作电压接近劣化电压。

公开(公告)号：US20120295414A1

公开(公告)日：2012-11-22

申请号：US13561990

申请日：2012-07-30

申请人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

发明人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

IPC分类号： H01L21/76 ,  H01L21/8222

CPC分类号： H01L27/0259

摘要： Methods are provided for producing stacked electrostatic discharge (ESD) clamps. In one embodiment, the method includes providing a semiconductor substrate in which first and second serially-coupled transistors are formed. The first transistor includes a first well region having a first lateral edge partially forming the first transistor's base. The second transistor including a second well region having a second lateral edge partially forming the second transistor's base. Third and fourth well regions are formed in the first and second transistors, respectively, and extend a different distance into the substrate than do the well regions of the first and second transistors. The third well region has a third lateral edge separated from the first lateral edge by a first spacing dimension D1. The fourth well region has a fourth lateral edge separated from the second lateral edge by a second spacing dimension D2, which is different than D1.

摘要翻译： 提供了用于生产叠层静电放电（ESD）夹具的方法。 在一个实施例中，该方法包括提供形成第一和第二串联耦合晶体管的半导体衬底。 第一晶体管包括具有部分地形成第一晶体管的基极的第一侧边缘的第一阱区。 第二晶体管包括具有部分地形成第二晶体管的基极的第二横向边缘的第二阱区。 第三和第四阱区分别形成在第一和第二晶体管中，并且与第一和第二晶体管的阱区相比，延伸到衬底中的不同距离。 第三阱区域具有与第一侧边缘分开第一间隔尺寸D1的第三横向边缘。 第四阱区具有与第二侧边缘分离第二间隔尺寸D2的第四横向边缘，其不同于D1。

公开(公告)号：US09502890B2

公开(公告)日：2016-11-22

申请号：US13900226

申请日：2013-05-22

申请人： Rouying Zhan ,  Chai Ean Gill ,  Wen-Yi Chen ,  Michael H. Kaneshiro

发明人： Rouying Zhan ,  Chai Ean Gill ,  Wen-Yi Chen ,  Michael H. Kaneshiro

IPC分类号： H01L29/66 ,  H01L27/02 ,  H02H9/04 ,  H01L29/732

CPC分类号： H02H9/044 ,  H01L27/0259 ,  H01L29/7322 ,  H02H9/046

摘要： Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a first base region of semiconductor material having a first conductivity type, a second base region of semiconductor material having the first conductivity type and a dopant concentration that is less than the first base region, a third base region of semiconductor material having the first conductivity type and a dopant concentration that is greater than the second base region, an emitter region of semiconductor material having a second conductivity type opposite the first conductivity type within the first base region, and a collector region of semiconductor material having the second conductivity type. At least a portion of the second base region resides between the third base region and the first base region and at least a portion of the first base region resides between the emitter region and the collector region.

摘要翻译： 提供了保护装置结构和相关制造方法。 一种示例性的半导体保护装置包括具有第一导电类型的半导体材料的第一基极区域，具有第一导电类型的第二基极区域和具有小于第一基极区域的掺杂剂浓度的第二基极区域，半导体的第三基极区域 具有第一导电类型和大于第二基极区的掺杂剂浓度的材料，具有与第一基极区内的第一导电类型相反的第二导电类型的半导体材料的发射极区域和具有第一导电类型的半导体材料的集电极区域， 第二导电类型。 第二基极区域的至少一部分位于第三基极区域和第一基极区域之间，并且第一基极区域的至少一部分位于发射极区域和集电极区域之间。

公开(公告)号：US20160005730A1

公开(公告)日：2016-01-07

申请号：US14854366

申请日：2015-09-15

申请人： Rouying Zhan ,  Chai Ean Gill ,  Changsoo Hong ,  Michael H. Kaneshiro

发明人： Rouying Zhan ,  Chai Ean Gill ,  Changsoo Hong ,  Michael H. Kaneshiro

IPC分类号： H01L27/02 ,  H01L27/082 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L27/0259 ,  H01L23/60 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/082 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/66234 ,  H01L29/6625 ,  H01L29/73 ,  H01L29/7317 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well implantation procedure implants dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions. The inner sinker region is configured to establish a common collector region of first and second bipolar transistor devices. A second well implantation procedure implants dopant of the first conductivity type in the semiconductor layer to form respective base regions of the first and second bipolar transistor devices. Conduction of the first bipolar transistor device is triggered by breakdown between the inner sinker region and the base region of the first bipolar transistor device. Conduction of the second bipolar transistor device is triggered by breakdown between the outer sinker region and the base region of the second bipolar transistor device.

摘要翻译： 在包括具有第一导电类型的半导体层的半导体衬底中制造ESD保护器件。 第一阱注入程序在半导体层中注入第二导电类型的掺杂剂以形成内部和外部沉降片区域。 内沉陷区域被配置成建立第一和第二双极晶体管器件的公共集电极区域。 第二阱注入步骤在半导体层中注入第一导电类型的掺杂剂以形成第一和第二双极晶体管器件的相应基极区。 第一双极晶体管器件的导通由第一双极晶体管器件的内部沉降区域和基极区域之间的击穿触发。 第二双极晶体管器件的导通由第二双极晶体管器件的外部沉降区域和基极区域之间的击穿触发。

公开(公告)号：US09129806B2

公开(公告)日：2015-09-08

申请号：US13900256

申请日：2013-05-22

申请人： Rouying Zhan ,  Chai Ean Gill ,  Wen-Yi Chen ,  Michael H. Kaneshiro

发明人： Rouying Zhan ,  Chai Ean Gill ,  Wen-Yi Chen ,  Michael H. Kaneshiro

IPC分类号： H01L29/74 ,  H01L29/66 ,  H01L27/02

CPC分类号： H01L27/0259

摘要： Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base well region having a first conductivity type, an emitter region within the base well region having a second conductivity type opposite the first conductivity type, a collector region having the second conductivity type, a first floating region having the second conductivity type within the base well region between the emitter region and the collector region, and a second floating region having the first conductivity type within the base well region between the first floating region and the collector region. The floating regions within the base well region are electrically connected to reduce current gain and improve holding voltage.

摘要翻译： 提供了保护装置结构和相关制造方法。 示例性的半导体保护装置包括具有第一导电类型的基极阱区域，在基极阱区域内的发射极区域具有与第一导电类型相反的第二导电类型，具有第二导电类型的集电极区域，具有第二导电类型的第一浮动区域， 在发射极区域和集电极区域之间的基极阱区域内的第二导电类型，以及在第一浮动区域和集电极区域之间的基极阱区域内具有第一导电类型的第二浮动区域。 基极区域内的浮动区域电连接以减小电流增益并改善保持电压。

公开(公告)号：US20150102384A1

公开(公告)日：2015-04-16

申请号：US14053716

申请日：2013-10-15

申请人： Rouying Zhan ,  Chai Ean Gill ,  Changsoo Hong ,  Michael H. Kaneshiro

发明人： Rouying Zhan ,  Chai Ean Gill ,  Changsoo Hong ,  Michael H. Kaneshiro

IPC分类号： H01L27/02 ,  H01L23/60 ,  H01L29/66

CPC分类号： H01L27/0259 ,  H01L23/60 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/082 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/66234 ,  H01L29/6625 ,  H01L29/73 ,  H01L29/7317 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) protection device includes a semiconductor substrate comprising a buried insulator layer and a semiconductor layer over the buried insulator layer having a first conductivity type, and first and second bipolar transistor devices disposed in the semiconductor layer, laterally spaced from one another, and sharing a common collector region having a second conductivity type. The first and second bipolar transistor devices are configured in an asymmetrical arrangement in which the second bipolar transistor device includes a buried doped layer having the second conductivity type and extending along the buried insulator layer from the common collector region across a device area of the second bipolar transistor device.

摘要翻译： 静电放电（ESD）保护装置包括半导体衬底，该半导体衬底包括掩埋绝缘体层和在具有第一导电类型的掩埋绝缘体层上的半导体层，以及设置在半导体层中的彼此横向间隔开的第一和第二双极晶体管器件 并且共享具有第二导电类型的公共收集器区域。 第一和第二双极晶体管器件被配置成非对称布置，其中第二双极晶体管器件包括具有第二导电类型的掩埋掺杂层，并且沿着埋在绝缘体层的跨第二极二极管的器件区域的公共集电极区域延伸 晶体管器件。

公开(公告)号：US08921942B2

公开(公告)日：2014-12-30

申请号：US13561990

申请日：2012-07-30

申请人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

发明人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

IPC分类号： H01L27/02

CPC分类号： H01L27/0259

摘要： Methods are provided for producing stacked electrostatic discharge (ESD) clamps. In one embodiment, the method includes providing a semiconductor substrate in which first and second serially-coupled transistors are formed. The first transistor includes a first well region having a first lateral edge partially forming the first transistor's base. The second transistor including a second well region having a second lateral edge partially forming the second transistor's base. Third and fourth well regions are formed in the first and second transistors, respectively, and extend a different distance into the substrate than do the well regions of the first and second transistors. The third well region has a third lateral edge separated from the first lateral edge by a first spacing dimension D1. The fourth well region has a fourth lateral edge separated from the second lateral edge by a second spacing dimension D2, which is different than D1.

摘要翻译： 提供了用于生产叠层静电放电（ESD）夹具的方法。 在一个实施例中，该方法包括提供形成第一和第二串联耦合晶体管的半导体衬底。 第一晶体管包括具有部分地形成第一晶体管的基极的第一侧边缘的第一阱区。 第二晶体管包括具有部分地形成第二晶体管的基极的第二横向边缘的第二阱区。 第三和第四阱区分别形成在第一和第二晶体管中，并且与第一和第二晶体管的阱区相比，延伸到衬底中的不同距离。 第三阱区域具有与第一侧边缘分开第一间隔尺寸D1的第三横向边缘。 第四阱区具有与第二侧边缘分离第二间隔尺寸D2的第四横向边缘，其不同于D1。

公开(公告)号：US08390071B2

公开(公告)日：2013-03-05

申请号：US12956686

申请日：2010-11-30

申请人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

发明人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

IPC分类号： H01L23/62 ,  H01L21/8222

CPC分类号： H01L21/8228 ,  H01L27/0259 ,  H01L29/66234

摘要： A stackable electrostatic discharge (ESD) protection clamp (21) for protecting a circuit core (24) comprises, a bipolar transistor (56, 58) having a base region (74, 51, 52, 85) with a base contact (77) therein and an emitter (78) spaced a lateral distance Lbe from the base contact (77), and a collector (80, 86, 762) proximate the base region (74, 51, 52, 85). The base region (74, 51, 52, 85) comprises a first portion (51) including the base contact (77) and emitter (78), and a second portion (52) with a lateral boundary (752) separated from the collector (86, 762) by a breakdown region (84) whose width D controls the clamp trigger voltage, the second portion (52) lying between the first portion (51) and the boundary (752). The damage-onset threshold current It2 of the ESD clamp (21) is improved by increasing the parasitic resistance Rbe of the emitter-base region (74, 51, 52, 85), by for example, increasing Lbe or decreasing the relative doping density of the first portion (51) or a combination thereof.

摘要翻译： 用于保护电路芯（24）的可堆叠静电放电（ESD）保护夹具（21）包括：具有基部接触（77）的基极区域（74,51,52,85）的双极晶体管（56,58） 以及与基部触点（77）间隔开横向距离Lbe的发射器（78）和靠近基部区域（74,51,52,85）的收集器（80,86,762）。 基部区域（74,51,52,85）包括包括基部触头（77）和发射极（78）的第一部分（51）和具有与集电器分离的侧边界（752）的第二部分（52） （86,762）由其宽度D控制钳位触发电压的击穿区域（84），第二部分（52）位于第一部分（51）和边界（752）之间。 通过增加发射极 - 基极区（74,51,52,85）的寄生电阻Rbe，例如增加Lbe或减小相对掺杂密度来改善ESD钳位（21）的损伤起始阈值电流It2 的第一部分（51）或其组合。