公开(公告)号：US20180052733A1

公开(公告)日：2018-02-22

申请号：US15676623

申请日：2017-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： DONGHWAN LEE ,  SAE-YOUNG CHUNG ,  LANYING ZHAO ,  SUNGIK CHOI ,  JUNJIN KONG ,  CHANGKYU SEOL ,  HYEJEONG SO ,  HONG RAK SON

IPC: G06F11/10

CPC classification number: G06F11/1072

Abstract: A method of decoding may include performing fewer than ⌊ 2 k - 1 k ⌋ number of sensing operations of multilevel cells within a nonvolatile memory device, decoding pages corresponding to each of the sensing operations while correcting a channel error using an RIO code, and extracting user data from the decoded pages.

公开(公告)号：US20150058536A1

公开(公告)日：2015-02-26

申请号：US14308739

申请日：2014-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANGKYU SEOL ,  JUNJIN KONG ,  HYEJEONG SO ,  HONG RAK SON

IPC: G06F12/02

CPC classification number: G11C11/5621 ,  G06F12/0246 ,  G06F2212/72

Abstract: A memory controller includes a state shaping encoder that receives k-bit write data, selects a logical page with reference to state shape mapping information, and changes data of the logical page to decrease an occurrence probability of a high-order program state among program states used to program the k-bit data in multi-level memory cells.

Abstract translation: 存储器控制器包括接收k位写入数据的状态整形编码器，参考状态形状映射信息选择逻辑页面，并且改变逻辑页面的数据，以减少程序状态之间高阶编程状态的发生概率 用于对多级存储单元中的k位数据进行编程。

公开(公告)号：US20150029789A1

公开(公告)日：2015-01-29

申请号：US14512965

申请日：2014-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANGKYU SEOL ,  EUNCHEOL KIM ,  JUNJIN KONG ,  HONG RAK SON

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5641 ,  H01L27/11578

Abstract: A nonvolatile memory device includes a memory cell array having multiple memory blocks. Each memory block includes memory cells arranged at intersections of multiple word lines and multiple bit lines. At least one word line of the multiple word lines is included in an upper word line group and at least one other word line of the multiple word lines is included in a lower word line group. The number of data bits stored in memory cells connected to the at least one word line included in the upper word line group is different from the number of data bits stored in memory cells connected to the at least one other word line included in the lower word line group.

Abstract translation: 非易失性存储器件包括具有多个存储块的存储单元阵列。 每个存储块包括布置在多个字线和多个位线的交点处的存储器单元。 多个字线的至少一个字线被包括在上部字线组中，并且多个字线的至少一个其它字线被包括在下部字线组中。 连接到包括在上部字线组中的至少一个字线的存储器单元中存储的数据位的数量不同于存储在连接到包含在下一个字中的至少一个其它字线的存储器单元中的数据位的数量 线组。

公开(公告)号：US20140025887A1

公开(公告)日：2014-01-23

申请号：US13935593

申请日：2013-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： KWANGHOON KIM ,  JUNJIN KONG ,  HONG RAK SON

IPC: G06F3/06

CPC classification number: G06F3/0689 ,  G06F3/0619 ,  G06F3/0665 ,  G06F11/108

Abstract: A method of operating a nonvolatile memory device comprising a plurality of memory blocks comprises storing first data and second data to be stored in a hot memory block of the memory blocks in a first buffer, transferring the first data stored in the first buffer to a second buffer to program the first data in the hot memory block, and generating RAID parity data based on the first and second data, wherein the RAID parity data and the first data form part of the same write stripe.

Abstract translation: 一种操作包括多个存储器块的非易失性存储器件的方法包括将第一数据和第二数据存储在存储器块的热存储块中的第一缓冲器中，将存储在第一缓冲器中的第一数据传送到第二缓冲器 缓冲器，用于对所述热存储器块中的第一数据进行编程，以及基于所述第一和第二数据生成RAID奇偶校验数据，其中所述RAID奇偶校验数据和所述第一数据形成相同写入条带的一部分。

公开(公告)号：US20130326296A1

公开(公告)日：2013-12-05

申请号：US13788592

申请日：2013-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEONGHYEOG CHOI ,  JUNJIN KONG ,  CHANGKYU SEOL ,  HONG RAK SON

IPC: G11C29/50

CPC classification number: G11C29/50004 ,  G06F11/1048 ,  G11C2029/0411

Abstract: A data processing method is provided for processing data read from a nonvolatile memory. The data processing method includes receiving first bit data from the nonvolatile memory at a memory controller, and performing erasure decoding based on the first bit data and second bit data stored in the memory controller. The first bit data indicates a memory cell that is erasure, and the second bit data is read using a read voltage during previous error correction decoding.

Abstract translation: 提供了一种用于处理从非易失性存储器读取的数据的数据处理方法。 数据处理方法包括在存储器控制器处从非易失性存储器接收第一位数据，并且基于存储在存储器控制器中的第一位数据和第二位数据执行擦除解码。 第一位数据指示擦除的存储单元，并且在先前纠错解码期间使用读取电压读取第二位数据。