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    INTEGRATED CIRCUIT INCLUDING READ ONLY MEMORY (ROM) CELL
    21.
    发明公开
    INTEGRATED CIRCUIT INCLUDING READ ONLY MEMORY (ROM) CELL 审中-公开

    公开(公告)号：US20240349497A1

    公开(公告)日：2024-10-17

    申请号：US18637013

    申请日：2024-04-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Suk YOUN ,  Taehyung KIM ,  Hoyoung TANG

    IPC: H10B20/00

    CPC classification number: H10B20/387

    Abstract: An integrated circuit includes a read only memory (ROM) cell which includes an on-cell. The on-cell includes: a first source/drain region and a second source/drain region; a frontside contact between the first source/drain region and a bit line on a front side of the on-cell; and a backside contact between the second source/drain region and a power line on a back side of the on-cell. The bit line is configured to provide a bit line signal to the on-cell, and the power line is configured to provide a power supply voltage signal to the on-cell. The bit line and the power line are vertically aligned with each other.

    INTEGRATED CIRCUIT INCLUDING BACKSIDE WIRING AND METHOD OF DESIGNING THE SAME
    25.
    发明公开
    INTEGRATED CIRCUIT INCLUDING BACKSIDE WIRING AND METHOD OF DESIGNING THE SAME 审中-公开

    公开(公告)号：US20240120258A1

    公开(公告)日：2024-04-11

    申请号：US18373709

    申请日：2023-09-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taehyung KIM ,  Hoyoung Tang ,  Yunsick Park

    IPC: H01L23/48 ,  H10B10/00

    CPC classification number: H01L23/481 ,  H10B10/125 ,  H10B10/18

    Abstract: Provided is an integrated circuit including a cell region in which a plurality of cells are arranged, and a peripheral region in which a circuit configured to control the plurality of cells is arranged, wherein the cell region further includes a plurality of first gate lines over a substrate, a plurality of first patterns in a first wiring layer above the plurality of first gate lines, a plurality of second patterns extending in a first horizontal direction in a backside wiring layer under the substrate, and a plurality of first vias, each of the plurality of first vias passing through the substrate in a vertical direction, wherein each of the plurality of first vias includes a top surface connected to a respective one of the plurality of first patterns and a bottom surface connected to a respective one of the plurality of second patterns.

    UNDER-DISPLAY CAMERA
    29.
    发明申请
    UNDER-DISPLAY CAMERA 有权

    公开(公告)号：US20220206545A1

    公开(公告)日：2022-06-30

    申请号：US17461206

    申请日：2021-08-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungho CHA ,  Sungsu KIM ,  Taehyung KIM ,  Seunghyeok JUNE

    IPC: G06F1/16 ,  G06T7/80 ,  H04N17/00

    Abstract: An under-display camera is provided, wherein an image acquisition unit including the under-display camera is configured to generate an evaluation image based on a first light, by using an imaging unit including an image sensor. The first light is output by a light emitting unit, including a light source, and passes through a display panel. The under-display camera is controlled based on a result of evaluating a performance of the under-display camera, the result being obtained by calculating a feature value based on the evaluation image, calculating a reference value based on a reference image, and comparing the feature value with the reference value, the reference image being obtained based on a second light output by the light emitting unit, the second light not passing the display panel.

    SEMICONDUCTOR DEVICE
    30.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210057411A1

    公开(公告)日：2021-02-25

    申请号：US16864260

    申请日：2020-05-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taehyung KIM ,  Jinwoo JEONG ,  Jiwook KWON ,  Raheel AZMAT ,  Kwanyoung CHUN

    IPC: H01L27/092 ,  H01L23/528 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

    Abstract: A semiconductor device including a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction crossing the first direction; first to third power rails respectively connected to the first to third active patterns, wherein a width of the second active pattern in the first direction is at least two times a width of the first active pattern in the first direction and is at least two times a width of the third active pattern in the first direction, the first active pattern is not vertically overlapped with the first power rail, the second active pattern is vertically overlapped with the second power rail, and the third active pattern is not vertically overlapped with the third power rail.

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