公开(公告)号：US11069410B1

公开(公告)日：2021-07-20

申请号：US16985335

申请日：2020-08-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Hardwell Chibvongodze ,  Rajdeep Gautam

IPC: G11C16/10 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11597 ,  G11C17/16 ,  G11C17/18 ,  G11C16/04 ,  G11C16/26 ,  G11C11/22 ,  H01L27/112

Abstract: First alternating stacks of first insulating strips and first spacer material strips is formed in a first device region, second alternating stacks of second insulating strips and second spacer material strips are formed in a second device region. Each of the first line trenches is filled with a respective laterally alternating sequence of memory stack structures and first dielectric pillar structures to form a three-dimensional NAND memory. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements. Each of the second line trenches with a respective laterally alternating sequence of active region assemblies of lateral field effect transistors and second dielectric pillar structures to form a three-dimensional NOR memory. Each of the active region assemblies includes a source pillar, a drain pillar, and a tubular channel region. The spacer material strips include, or are subsequently replaced with, electrically conductive strips.

公开(公告)号：US20210173559A1

公开(公告)日：2021-06-10

申请号：US16704729

申请日：2019-12-05

Applicant: SanDisk Technologies LLC

Inventor： Masatoshi Nishikawa ,  Hardwell Chibvongodze

IPC: G06F3/06 ,  G06F13/16 ,  G11C16/24 ,  G11C16/14

Abstract: A method for memory block management includes identifying a first group of bit lines corresponding to memory blocks of a 3-dimensional memory array. The method also includes biasing the first group of bit lines to a first voltage using respective bit line biasing transistors. The method also includes identifying, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect the first group of bit lines. The method also includes logically grouping memory addresses of memory cells for each respective sub-memory block associated with the first group of bit lines.

公开(公告)号：US10971231B1

公开(公告)日：2021-04-06

申请号：US16912720

申请日：2020-06-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rajdeep Gautam ,  Hardwell Chibvongodze ,  Ken Oowada

IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/28

Abstract: Systems and methods for reducing program disturb when programming portions of a memory array are described. A memory array may include a first set of NAND strings and a second set of NAND strings that share a common bit line that is connected to the drain-side end of drain-side select gates of the NAND strings and/or share a common source-side select gate line that connects to the gates of source-side select gates of the NAND strings. During programming of the first set of NAND strings a first pass voltage (e.g., 7V) may be applied to unselected word lines of the memory array and subsequently during programming of the second set of NAND strings a second pass voltage (e.g., 9V) greater than the first pass voltage may be applied to the unselected word lines of the memory array.

公开(公告)号：US10741535B1

公开(公告)日：2020-08-11

申请号：US16275668

申请日：2019-02-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi Nishikawa ,  Hardwell Chibvongodze

IPC: H01L25/065 ,  G11C16/04 ,  H01L23/00 ,  H01L25/18 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556

Abstract: A first memory die includes an array of first memory stack structures and first bit lines. A second memory die includes an array of second memory stack structures and second bit lines electrically connected to a respective subset of the second drain regions. A support die is provided, which includes a peripheral circuitry for operating the array of first memory stack structures and the array of second memory stack structures. The peripheral circuitry includes a plurality of sense amplifiers configured to make switchable electrical connections to a set of bit lines selected from the first bit lines and the second bit lines. The first memory die is bonded to the support die, and the second memory die is bonded to the first memory die. The peripheral circuitry in the support die may be shared between the first memory die and the second memory die.