公开(公告)号：US20240055051A1

公开(公告)日：2024-02-15

申请号：US17888063

申请日：2022-08-15

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  YenLung Li ,  James Kai

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16

Abstract: Technology is disclosed herein reconfiguring word lines as either data word lines or dummy word lines. In a sub-block mode reconfigurable word lines are used as dummy word lines that provide electrical isolation between data word lines in a block. The block may be divided into an upper tier, a middle tier, and a lower tier, with the reconfigurable word lines within the middle tier. In a full-block mode the reconfigurable group of the word lines are used as data word lines. Because the reconfigurable word lines are used as data word lines in the full-block mode storage capacity is greater in the full-block mode than in the sub-block mode. Moreover, because the sub-blocks are smaller in size but greater in number than the full-blocks, the memory system may be provisioned with fewer blocks and still meet user storage requirements in both the full-block mode and the sub-block mode.

公开(公告)号：US11901019B2

公开(公告)日：2024-02-13

申请号：US17666657

申请日：2022-02-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hua-Ling Cynthia Hsu ,  Masaaki Higashitani ,  YenLung Li ,  Chen Chen

IPC: G11C16/26 ,  G11C16/24 ,  H03M13/00 ,  H03M13/11 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/24 ,  H03M13/1111 ,  H03M13/611

Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

公开(公告)号：US11776589B2

公开(公告)日：2023-10-03

申请号：US17731961

申请日：2022-04-28

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  YenLung Li

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/065 ,  G11C7/106 ,  G11C7/1012 ,  G11C7/1069 ,  G11C7/1087 ,  G11C7/12

Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

公开(公告)号：US11735288B1

公开(公告)日：2023-08-22

申请号：US17672904

申请日：2022-02-16

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  YenLung Li

IPC: G11C29/50

CPC classification number: G11C29/50004 ,  G11C2029/5004

Abstract: Technology is disclosed herein for loading redundancy information during a memory system power on read (POR). A memory structure has primary regions (e.g., primary columns) and a number of redundant regions (e.g., redundant columns). The status of the regions is stored in isolation latches during the POR. Initially, simultaneously all latches for primary regions are reset to used and all latches for redundant regions are reset to unused. Then, isolation latches for defective primary regions are set to unused while isolation latches for corresponding redundant regions are set to used. There is no need to individually set isolation latches for redundant regions to unused, which saves time during POR. Moreover, whenever the isolation latch for a defective primary region is set from used to unused, in parallel the isolation latch for the replacement redundant column may be set from unused to used, thereby not incurring a time penalty.

公开(公告)号：US11004535B1

公开(公告)日：2021-05-11

申请号：US16717494

申请日：2019-12-17

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  YenLung Li ,  Aaron Lee

IPC: G11C29/00 ,  G11C29/02 ,  G11C7/10 ,  G11C11/4094 ,  G11C11/408

Abstract: Apparatuses and techniques are described for reliably storing bad column data in a memory device. Units of bad column data and related units of error detection data are stored in non-adjacent groups of memory cells connected to a word line in a ROM block. A unit of bad column data and a related unit of error detection data can be stored in respective groups of memory cells which are relatively far apart from one another along the word line. This helps ensure that a defect in some NAND strings will not affect both the unit of bad column data and a related unit of error detection data. In another aspect, a unit of bad column data and a related unit of error detection data can be stored using different input/output circuits to further increase robustness.