公开(公告)号：US20240256033A1

公开(公告)日：2024-08-01

申请号：US18569785

申请日：2022-06-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiromichi GODO ,  Yoshiyuki KUROKAWA ,  Seiko INOUE ,  Kazuaki OHSHIMA ,  Shunpei YAMAZAKI

IPC: G06F3/01 ,  G06T1/20 ,  G06T7/73 ,  G06V10/141 ,  G06V40/18 ,  H04N23/611 ,  H04N23/617 ,  H04N23/90

CPC classification number: G06F3/013 ,  G06T1/20 ,  G06T7/75 ,  G06V10/141 ,  G06V40/193 ,  H04N23/611 ,  H04N23/617 ,  H04N23/90 ,  G06T2207/10048 ,  G06T2207/20081 ,  G06T2207/30041 ,  G06T2207/30201

Abstract: An electronic device that enables smooth communication is provided. The electronic device includes a display portion including a first camera; a second camera; and an image processing portion. The second camera is positioned in a region not overlapping with the display portion. The first camera has a function of generating a first image of a subject, and the second camera has a function of generating a second image of the subject. The image processing portion includes a generator that performs learning using training data. The training data includes an image including a person's face. The image processing portion has a function of making the first image clear when the first image is input to the generator and a function of tracking the gaze of the subject on the basis of the second image.

公开(公告)号：US20220382937A1

公开(公告)日：2022-12-01

申请号：US17776054

申请日：2020-11-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Seiko INOUE ,  Ryo NAKAZATO ,  Takahiro FUKUTOME

IPC: G06F30/27 ,  G06F30/398

Abstract: A novel circuit layout method is provided. In a circuit including a first terminal, a second terminal, a third terminal, a fourth terminal, a first wiring, and a second wiring, the layout method includes a step of generating a layout of connecting the first terminal and the third terminal using the first wiring; a step of generating a layout of connecting the second terminal and the fourth terminal using the second wiring; a step of calculating a first wiring resistance of the first wiring; a step of calculating a second wiring resistance of the second wiring; and a step of automatically generating the layouts of the first wiring and the second wiring in the circuit so that the first wiring resistance can be equal to the second wiring resistance.

公开(公告)号：US20220147106A1

公开(公告)日：2022-05-12

申请号：US17585680

申请日：2022-01-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiharu HIRAKATA ,  Hiroyuki MIYAKE ,  Seiko INOUE ,  Shunpei YAMAZAKI

IPC: G06F1/16 ,  G06F3/041

Abstract: A display device with low power consumption is provided. Furthermore, a display device in which an image is displayed in a region that can be used in a folded state is provided. The conceived display device includes a display portion that can be opened and folded, a sensing portion that senses a folded state of the display portion, and an image processing portion that generates, when the display portion is in the folded state, an image in which a black image is displayed in part of the display portion.

公开(公告)号：US20190227600A1

公开(公告)日：2019-07-25

申请号：US16367905

申请日：2019-03-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiharu HIRAKATA ,  Hiroyuki MIYAKE ,  Seiko INOUE ,  Shunpei YAMAZAKI

IPC: G06F1/16 ,  G06F3/041

Abstract: A display device with low power consumption is provided. Furthermore, a display device in which an image is displayed in a region that can be used in a folded state is provided. The conceived display device includes a display portion that can be opened and folded, a sensing portion that senses a folded state of the display portion, and an image processing portion that generates, when the display portion is in the folded state, an image in which a black image is displayed in part of the display portion.

公开(公告)号：US20190033919A1

公开(公告)日：2019-01-31

申请号：US15986099

申请日：2018-05-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiharu HIRAKATA ,  Hiroyuki MIYAKE ,  Seiko INOUE ,  Shunpei YAMAZAKI

IPC: G06F1/16 ,  G06F3/041

Abstract: A display device with low power consumption is provided. Furthermore, a display device in which an image is displayed in a region that can be used in a folded state is provided. The conceived display device includes a display portion that can be opened and folded, a sensing portion that senses a folded state of the display portion, and an image processing portion that generates, when the display portion is in the folded state, an image in which a black image is displayed in part of the display portion.

公开(公告)号：US20140361290A1

公开(公告)日：2014-12-11

申请号：US14290251

申请日：2014-05-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hiroyuki MIYAKE ,  Seiko INOUE ,  Shinpei MATSUDA ,  Daisuke MATSUBAYASHI ,  Masahiko HAYAKAWA

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/1251 ,  H01L27/3258 ,  H01L27/3262

Abstract: In a pixel including a selection transistor, a driver transistor, and a light-emitting element, as the driver transistor, a transistor is used in which a channel is formed in an oxide semiconductor film and its channel length is 0.5 μm or greater and 4.5 μm or less. The driver transistor includes a first gate electrode over an oxide semiconductor film and a second gate electrode below the oxide semiconductor film. The first gate electrode and the second gate electrode are electrically connected to each other and overlap with the oxide semiconductor film. Furthermore, in the selection transistor of a pixel, which does not need to have field-effect mobility as high as that of the driver transistor, a channel length is made longer than at least the channel length of the driver transistor.

Abstract translation: 在包括选择晶体管，驱动晶体管和发光元件的像素中，作为驱动晶体管，使用在氧化物半导体膜中形成沟道并且其沟道长度为0.5μm以上且4.5以下的晶体管 μm以下。 驱动晶体管包括氧化物半导体膜上的第一栅电极和氧化物半导体膜下方的第二栅电极。 第一栅电极和第二栅电极彼此电连接并与氧化物半导体膜重叠。 此外，在不需要具有与驱动晶体管的场效应迁移率一样高的像素的选择晶体管中，使沟道长度比驱动晶体管的沟道长度至少长。

公开(公告)号：US20140339543A1

公开(公告)日：2014-11-20

申请号：US14276356

申请日：2014-05-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hiroyuki MIYAKE ,  Seiko INOUE ,  Daisuke MATSUBAYASHI

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device includes a dual-gate transistor including an oxide semiconductor film between a first gate electrode and a second gate electrode, a gate insulating film between the oxide semiconductor film and the second gate electrode, and a pair of electrodes in contact with the oxide semiconductor film. The semiconductor device further includes an insulating film over the gate insulating film, and a conductive film over the insulating film and connected to one of the pair of electrodes. The insulating film includes an opening in at least a region overlapping with the oxide semiconductor film in which the second gate electrode is provided in contact with the gate insulating film. The second gate electrode is formed using the same material as the conductive film connected to the one of the pair of electrodes.

Abstract translation: 半导体器件包括双栅极晶体管，其包括在第一栅电极和第二栅电极之间的氧化物半导体膜，氧化物半导体膜和第二栅电极之间的栅极绝缘膜，以及与氧化物接触的一对电极 半导体膜。 所述半导体器件还包括位于所述栅极绝缘膜上的绝缘膜，以及在所述绝缘膜上的导电膜并且连接到所述一对电极之一。 所述绝缘膜在至少与所述氧化物半导体膜重叠的区域中具有开口，所述第二栅电极与所述栅极绝缘膜接触。 第二栅电极使用与连接到该对电极中的一个电极的导电膜相同的材料形成。