公开(公告)号：US20220115404A1

公开(公告)日：2022-04-14

申请号：US17561471

申请日：2021-12-23

Applicant: SK hynix Inc.

Inventor： Kun Young LEE ,  Sun Young KIM ,  Jae Gil LEE

IPC: H01L27/11597 ,  H01L27/1159

Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a stack including a conductive pattern and an insulating pattern, a channel structure penetrating the stack, and a memory pattern between the conductive pattern and the channel structure. The memory pattern includes a blocking pattern, a tunnel pattern, a storage pattern, and a ferroelectric pattern.

公开(公告)号：US20220013540A1

公开(公告)日：2022-01-13

申请号：US17484481

申请日：2021-09-24

Applicant: SK hynix Inc.

Inventor： Hyangkeun YOO ,  Ju Ry SONG ,  Se Ho LEE ,  Jae Gil LEE

IPC: H01L27/11582 ,  H01L29/10 ,  G11C16/14 ,  G11C16/04 ,  G11C16/10 ,  H01L29/267

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a channel structure extending in a direction perpendicular to the substrate; a charge storage structure disposed to be in contact with the channel structure; and a cell electrode structure disposed to be in contact with the charge storage structure in a lateral direction, wherein the channel structure comprises a hole conduction layer and an electron conduction layer.

公开(公告)号：US20210183890A1

公开(公告)日：2021-06-17

申请号：US17159979

申请日：2021-01-27

Applicant: SK hynix Inc.

Inventor： Jae Gil LEE ,  Ju Ry SONG ,  Hyangkeun YOO ,  Se Ho LEE

IPC: H01L27/11597 ,  H01L29/423 ,  H01L29/417 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

Abstract: In a method, a stack structure including a plurality of first interlayer sacrificial layers and a plurality of second interlayer sacrificial layers that are alternately stacked is formed over a substrate. A trench penetrating the stack structure is formed. A channel layer covering a sidewall surface of the trench is formed. The plurality of first interlayer sacrificial layers are selectively removed to form a plurality of first recesses. The plurality of first recesses are filled with a conductive material to form a plurality of channel contact electrode layers. The plurality of second interlayer sacrificial layers are selectively removed to form a plurality of second recesses. A plurality of interfacial insulation layers, a plurality of ferroelectric layers and a plurality of gate electrode layers are formed in the plurality of second recesses.

公开(公告)号：US20210111190A1

公开(公告)日：2021-04-15

申请号：US16888057

申请日：2020-05-29

Applicant: SK hynix Inc.

Inventor： Kun Young LEE ,  Sun Young KIM ,  Jae Gil LEE

IPC: H01L27/11597 ,  H01L27/1159

Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a stack including a conductive pattern and an insulating pattern, a channel structure penetrating the stack, and a memory pattern between the conductive pattern and the channel structure. The memory pattern includes a blocking pattern, a tunnel pattern, a storage pattern, and a ferroelectric pattern.

公开(公告)号：US20200212068A1

公开(公告)日：2020-07-02

申请号：US16536063

申请日：2019-08-08

Applicant: SK hynix Inc.

Inventor： Jae Gil LEE ,  Ju Ry SONG ,  Hyangkeun YOO ,  Se Ho LEE

IPC: H01L27/11597 ,  H01L29/423 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: A vertical memory device according to an aspect includes a substrate, a first gate electrode structure disposed on the substrate and a second gate electrode structure spaced apart from the first gate electrode structure in a first direction substantially perpendicular to the substrate, a channel contact electrode layer disposed between the first gate electrode structure and the second gate electrode structure, and a channel layer extending along the first direction and in contact with the channel contact electrode layers and the first and the second gate electrode structures.