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    NONVOLATILE MEMORY DEVICE HAVING MULTIPLE NUMBERS OF CHANNEL LAYERS
    1.
    发明申请
    NONVOLATILE MEMORY DEVICE HAVING MULTIPLE NUMBERS OF CHANNEL LAYERS 审中-公开

    公开(公告)号：US20200212060A1

    公开(公告)日：2020-07-02

    申请号：US16558678

    申请日：2019-09-03

    Applicant: SK hynix Inc.

    Inventor： Hyangkeun YOO ,  Ju Ry SONG ,  Se Ho LEE ,  Jae Gil LEE

    IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/267 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14

    Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a cell electrode structure disposed on the substrate and including interlayer insulating layers and gate electrode layers that are alternately stacked, a trench penetrating the cell structure on the substrate, a charge storage structure disposed on a sidewall surface of the trench, and a channel structure disposed adjacent to the charge storage structure and extending in a direction parallel to the sidewall surface. The channel structure includes a separate hole conduction layer and an adjacent and separate electron conduction layer. A control channel layer disposed on a control dielectric layer is a portion of the electron conduction layer configured to electrically connect to the channel structure, and to the charge storage structure. A control dielectric layer and a charge barrier layer are discrete but contiguous from the control channel structure to the charge storage structure.

    METHOD OF FORMING PATTERNS USING REVERSE PATTERNS
    3.
    发明申请
    METHOD OF FORMING PATTERNS USING REVERSE PATTERNS 有权

    公开(公告)号：US20220005695A1

    公开(公告)日：2022-01-06

    申请号：US17154298

    申请日：2021-01-21

    Applicant: SK hynix Inc.

    Inventor： Jung Hyung LEE ,  Sarohan PARK ,  Ju Ry SONG ,  Ji Young IM ,  Sang Hee JUNG

    IPC: H01L21/033 ,  H01L21/311 ,  H01L21/027

    Abstract: In a method of forming patterns, first and second upper reverse patterns are formed on a lower reverse layer. A buffer layer is formed to fill first opening portions provided by the first upper reverse pattern. A shield pattern is formed to cover a second region of the buffer layer. An etching process is performed using the shield pattern and the first upper reverse pattern as an etching mask to form first lower reverse patterns providing second openings overlapping first openings, a buffer layer pattern and a second lower reverse pattern overlapping the shield pattern. A hard mask layer is formed and etched to separate hard mask layer first patterns filling the first and second openings. An etching process is performed using the hard mask layer first patterns and the second upper reverse patterns as etching masks to form third lower reverse patterns overlapping the second upper reverse pattern.

    METHOD OF FABRICATING VERTICAL MEMORY DEVICE
    4.
    发明申请
    METHOD OF FABRICATING VERTICAL MEMORY DEVICE 有权

    公开(公告)号：US20210183890A1

    公开(公告)日：2021-06-17

    申请号：US17159979

    申请日：2021-01-27

    Applicant: SK hynix Inc.

    Inventor： Jae Gil LEE ,  Ju Ry SONG ,  Hyangkeun YOO ,  Se Ho LEE

    IPC: H01L27/11597 ,  H01L29/423 ,  H01L29/417 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

    Abstract: In a method, a stack structure including a plurality of first interlayer sacrificial layers and a plurality of second interlayer sacrificial layers that are alternately stacked is formed over a substrate. A trench penetrating the stack structure is formed. A channel layer covering a sidewall surface of the trench is formed. The plurality of first interlayer sacrificial layers are selectively removed to form a plurality of first recesses. The plurality of first recesses are filled with a conductive material to form a plurality of channel contact electrode layers. The plurality of second interlayer sacrificial layers are selectively removed to form a plurality of second recesses. A plurality of interfacial insulation layers, a plurality of ferroelectric layers and a plurality of gate electrode layers are formed in the plurality of second recesses.

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