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公开(公告)号：US10050607B2
公开(公告)日：2018-08-14
申请号：US14573055
申请日：2014-12-17
Applicant: STMicroelectronics International N.V.
Inventor： Neha Bhargava , Ankur Bal
Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.
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公开(公告)号：US20170294898A1
公开(公告)日：2017-10-12
申请号：US15632202
申请日：2017-06-23
Applicant: STMicroelectronics International N.V.
Inventor： Neha Bhargava , Ankur Bal
CPC classification number: H03H17/0283 , H03H17/0275 , H03H17/0664 , H03H17/0671 , H03H21/0027 , H03H2017/0245
Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.
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公开(公告)号：US09379728B1
公开(公告)日：2016-06-28
申请号：US14751456
申请日：2015-06-26
Applicant: STMicroelectronics International N.V.
Inventor： Pratap Narayan Singh , Shiva Sharath Babu Kaleru , Ankur Bal , Mohit Singh , Rakesh Malik
CPC classification number: H03M1/1023 , H03M1/1047 , H03M1/66
Abstract: A digital-to-analog converter has an output. An analog-to-digital converter senses a voltage at the output of the digital-to-analog converter and generates a digital voltage signal. A source mismatch estimator processes the digital voltage signal to output an error signal indicative of current source mismatch within the digital-to-analog converter. An error code generator generates a digital calibration signal from the error signal. The digital calibration signal is converted by a redundancy digital-to-analog converter to an analog compensation signal for application to the output of analog-to-digital converter to nullify effects of the current source mismatch.
Abstract translation: 一个数模转换器有一个输出。 模拟 - 数字转换器感测数模转换器输出端的电压，并产生一个数字电压信号。 源不匹配估计器处理数字电压信号以输出指示数模转换器内的电流源失配的误差信号。 错误代码发生器从误差信号产生数字校准信号。 数字校准信号由冗余数模转换器转换为模拟补偿信号，以应用于模数转换器的输出，以消除电流源不匹配的影响。
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公开(公告)号：US12086568B2
公开(公告)日：2024-09-10
申请号：US18134737
申请日：2023-04-14
Applicant: STMicroelectronics International N.V.
Inventor： Ankur Bal , Rupesh Singh
CPC classification number: G06F7/548 , G06F7/5443 , H03K3/037 , H03K5/01 , H03K2005/00078
Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.
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公开(公告)号：US12055989B2
公开(公告)日：2024-08-06
申请号：US17194037
申请日：2021-03-05
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Ankur Bal , Vikas Chelani
Abstract: An integrated circuit includes a plurality of flip-flops and a global reset network for resetting the flip-flops. The integrated circuit includes a synchronous clock delay circuit that delays, responsive to a global reset signal, a transition in a clock signal provided to the flip-flops. The delay in the transition of the clock signal ensures that all of the flip-flops receive the global reset signal within a same delayed clock cycle and that the flip-flops do not receive the global reset signal during a rising or falling edge of the clock signal.
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Patent Agency Ranking
公开(公告)号：US11933861B2
公开(公告)日：2024-03-19
申请号：US17860959
申请日：2022-07-08
Applicant: STMicroelectronics International N.V.
Inventor： Ankur Bal , Sharad Gupta
IPC: G01R31/40
CPC classification number: G01R31/40
Abstract: A method and apparatus for performing an on-system built-in self-test of a converter are provided. In the method, a controller generates a test signal and outputs the test signal to the converter. The controller receives a response signal from the converter and determines a plurality of bin powers of a plurality of bins, respectively, of a frequency domain signal representative of the response signal. The controller determines a figure of merit for the converter based on a first bin power of a first bin of the plurality of bin powers, where the first bin corresponds to a frequency of the test signal.
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公开(公告)号：US11909410B2
公开(公告)日：2024-02-20
申请号：US17982242
申请日：2022-11-07
Applicant: STMicroelectronics International N.V.
Inventor： Ankur Bal , Sharad Gupta
CPC classification number: H03M1/0809 , H03M1/0626 , H03M1/0648 , H03M1/1014
Abstract: An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.
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公开(公告)号：US20190190688A1
公开(公告)日：2019-06-20
申请号：US15846560
申请日：2017-12-19
Applicant: STMicroelectronics International N.V.
Inventor： Rupesh Singh , Ankur Bal
IPC: H04L7/00
Abstract: Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.
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29.发明申请公开(公告)号：US20190158070A1
公开(公告)日：2019-05-23
申请号：US15815989
申请日：2017-11-17
Applicant: STMicroelectronics International N.V.
Inventor： Mohit Singh , Ankur Bal
IPC: H03H17/06
Abstract: A digital filtering method includes receiving a digital signal, and passing the digital signal through a Pth order comb cascade. The method includes beginning pre-computing of intermediate integrator states of a Pth order integrator cascade as a function of the digital signal, prior to receiving output from a last comb of the Pth order comb cascade. The outputs from each comb of the Pth order comb cascade are then applied to the pre-computed intermediate integrator states to thereby produce a filtered version of the digital signal. The Pth order comb cascade may operate at a sampling frequency, and the pre-computing of the intermediate integrator states is performed at the sampling frequency, while the application of the outputs from each comb of the Pth order comb cascade to the pre-computed intermediate integrator states is performed at a multiple of the sampling frequency.
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公开(公告)号：US10218380B1
公开(公告)日：2019-02-26
申请号：US16036004
申请日：2018-07-16
Applicant: STMicroelectronics International N.V.
Inventor： Ankur Bal , Rupesh Singh
Abstract: Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.
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