公开(公告)号：US11656848B2

公开(公告)日：2023-05-23

申请号：US16988912

申请日：2020-08-10

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Rupesh Singh

IPC: G06F7/48 ,  G06F7/548 ,  H03K3/037 ,  G06F7/544 ,  H03K5/01 ,  H03K5/00

CPC classification number: G06F7/548 ,  G06F7/5443 ,  H03K3/037 ,  H03K5/01 ,  H03K2005/00078

Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.

公开(公告)号：US11417371B2

公开(公告)日：2022-08-16

申请号：US17374304

申请日：2021-07-13

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Rupesh Singh ,  Vivek Tripathi

IPC: G11C7/10 ,  H03L7/107 ,  G11C7/22 ,  H03M1/00 ,  G11C7/04

Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.

公开(公告)号：US20210119621A1

公开(公告)日：2021-04-22

申请号：US17029631

申请日：2020-09-23

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Vikas Chelani

IPC: H03K5/1252

Abstract: A debounce circuit and a method for masking or filtering a glitch from an input signal are provided. The debounce circuit includes a reset synchronizer circuit and a logic circuit. The reset synchronizer circuit receives the input signal, detects a glitch in the input signal and outputs one or more reset synchronizer output signals having a first reset synchronizer state indicating detection of the glitch. The logic circuit receives the one or more reset synchronizer output signals, determines that the one or more reset synchronizer output signals are in the first reset synchronizer state indicating detection of the glitch and in response to determining that the one or more reset synchronizer output signals are in the first reset synchronizer state, keeps an output signal of the debounce circuit in a present state of the output signal of the debounce circuit.

公开(公告)号：US10484165B2

公开(公告)日：2019-11-19

申请号：US15846560

申请日：2017-12-19

Applicant: STMicroelectronics International N.V.

Inventor： Rupesh Singh ,  Ankur Bal

IPC: H04L7/00

Abstract: Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.

公开(公告)号：US09780803B1

公开(公告)日：2017-10-03

申请号：US15266445

申请日：2016-09-15

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Chandrajit Debnath ,  Neha Bhargava

IPC: H03M1/10 ,  H03M3/00

CPC classification number: H03M1/1071 ,  H03M3/344 ,  H03M3/378 ,  H03M3/414 ,  H03M3/422 ,  H03M3/464

Abstract: A built-in self-test (BIST) circuit is provided for testing an analog-to-digital converter (ADC). A multi-order sigma-delta (ΣΔ) modulator has an input that receives an input signal, a first output generating analog test signal derived from the input signal and applied to an input of the ADC and a second output generating a binary data stream. A digital recombination and filtering circuit has a first input that receives the binary data stream and a second input that receives a digital test signal output from the ADC in response to the analog test signal. The digital recombination and filtering circuit combines and filters the binary data stream and digital test signal to generate a digital result signal including a signal component derived from an error introduced by operation of the ADC. A correlation circuit is used to isolate that error signal component.

公开(公告)号：US20170249931A1

公开(公告)日：2017-08-31

申请号：US15595639

申请日：2017-05-15

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Anupam Jain ,  Rakhel Kumar Parida

IPC: G10K11/00 ,  G10L21/0232 ,  H04L25/03 ,  G10L21/0208

CPC classification number: G10K11/002 ,  G10L21/0208 ,  G10L21/0232 ,  H04L5/0008 ,  H04L25/03159 ,  H04L27/2649 ,  H04L2025/03414

Abstract: A system for noise removal is coupled to a signal unit that provides a digital signal. The noise removal system includes a transformation module to transform the digital signal into an f-digital signal, a threshold filter to generate a noiseless signal from the f-digital signal based on a threshold profile, and a signal synthesizer to provide a gain to the noiseless signal and to transform the noiseless signal into an output signal.

公开(公告)号：US12210373B2

公开(公告)日：2025-01-28

申请号：US18165855

申请日：2023-02-07

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Sharad Gupta ,  Anupam Jain

IPC: G06F1/12 ,  G06F1/08 ,  G06F1/10

Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem includes an edge detector configured to detect an edge of the second clock signal. The first clock generator generates the first clock signal with a selected phase relative to the second clock signal based on the edge of the second clock signal.

公开(公告)号：US12088326B2

公开(公告)日：2024-09-10

申请号：US17940236

申请日：2022-09-08

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Abhishek Jain

IPC: H03M3/00 ,  H03K3/356 ,  H03M1/06

CPC classification number: H03M3/464 ,  H03K3/356 ,  H03M1/0626 ,  H03M3/43

Abstract: A continuous time, sigma-delta analog-to-digital converter circuit includes a sigma-delta modulator circuit configured to receive an analog input signal. A single bit quantizer of the modulator generates a digital output signal at a sampling frequency. A data storage circuit stores bits of the digital output signal and digital-to-analog converter (DAC) elements are actuated in response to the stored bits to generate an analog feedback signal for comparison to the analog input signal. A filter circuit includes polyphase signal processing paths and a summation circuit configured to sum outputs from the polyphase signal processing paths to generate a converted output signal. A fan out circuit selectively applies the stored bits from the data storage circuit to inputs of the polyphase signal processing paths of the filter circuit.

公开(公告)号：US20230024278A1

公开(公告)日：2023-01-26

申请号：US17860959

申请日：2022-07-08

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Sharad Gupta

IPC: G01R31/40

Abstract: A method and apparatus for performing an on-system built-in self-test of a converter are provided. In the method, a controller generates a test signal and outputs the test signal to the converter. The controller receives a response signal from the converter and determines a plurality of bin powers of a plurality of bins, respectively, of a frequency domain signal representative of the response signal. The controller determines a figure of merit for the converter based on a first bin power of a first bin of the plurality of bin powers, where the first bin corresponds to a frequency of the test signal.

公开(公告)号：US11463098B2

公开(公告)日：2022-10-04

申请号：US17342416

申请日：2021-06-08

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Ankur Bal ,  Sri Ram Gupta ,  Rupesh Singh

IPC: H03M1/10 ,  H03M1/38 ,  H03M1/46

Abstract: An integrated circuit includes a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC includes a bit step selector. During testing of the ADC, the bit step selector selects a number of bits to be tested for a next analog test voltage based on digital values that are within an integer delta value of most recent digital value for a most recent analog test voltage.