公开(公告)号：US20240154618A1

公开(公告)日：2024-05-09

申请号：US18300692

申请日：2023-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungkeun YOON ,  Seijoon KIM ,  Hyunsoo KIM ,  Chang-Woo SHIN

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/46

CPC classification number: H03M1/0648 ,  H03M1/125 ,  H03M1/462

Abstract: A method of optimizing a quantization step size of an analog-to-digital converter (ADC) based on a number of crossbar arrays of a computing device includes: generating a first mapping relationship between the quantization step size of the ADC and a first root mean square error, the first root mean square error reflecting a quantization error and a clipping error, wherein the generating the first graph is based on use of only a single crossbar array; generating a second mapping relationship between the quantization step size of the ADC and a second root mean square error, the second root mean square error reflecting a quantization error, wherein the generating the second mapping is based on a uniform distribution of a total sum of quantization errors; and determining the quantization step size of the ADC based on the first mapping relationship and the second mapping relationship.

公开(公告)号：US09184974B1

公开(公告)日：2015-11-10

申请号：US14316112

申请日：2014-06-26

Applicant: The Boeing Company

Inventor： Cynthia D. Baringer ,  Donald A. Hitko

IPC: H04L27/36 ,  H04L27/26

CPC classification number: H04L27/362 ,  H03M1/0648 ,  H03M1/74 ,  H04L27/206 ,  H04L27/2637

Abstract: Disclosed herein is an apparatus for radio frequency digital-to-analog conversion of in-phase and quadrature bit streams. The apparatus may include a plurality of in-phase multiplying cells that receive an in-phase local oscillator signal and a plurality of in-phase bits, a plurality of quadrature multiplying cells that receive a quadrature local oscillator signal and a plurality of quadrature bits, a first output line connected to a first set of the plurality of in-phase multiplying cells and a first set of the plurality of quadrature multiplying cells, and a second output line connected to a second set of the plurality of in-phase multiplying cells and a second set of the plurality of quadrature multiplying cells. Each multiplying cell produces an output signal based on a received input bit. The output signals from each multiplying cell combine in phase on the connected output line.

Abstract translation: 本文公开了一种用于同相和正交比特流的射频数模转换的装置。 该装置可以包括接收同相本地振荡器信号和多个同相位的多个同相乘法单元，接收正交本地振荡器信号和多个正交位的多个正交乘法单元， 连接到所述多个同相乘法单元的第一组的第一输出线和所述多个正交乘法单元的第一组，以及连接到所述多个同相乘法单元的第二组的第二输出线，以及 所述多个正交倍增单元的第二组。 每个乘法单元基于接收的输入位产生输出信号。 来自每个乘法单元的输出信号在连接的输出线上同相组合。

公开(公告)号：US20150214975A1

公开(公告)日：2015-07-30

申请号：US14243105

申请日：2014-04-02

Applicant: BROADCOM CORPORATION

Inventor： Ramon Alejandro Gomez ,  Thomas Joseph Kolze ,  Bruce Joseph Currivan

IPC: H03M1/66

CPC classification number: H03M1/742 ,  H03M1/002 ,  H03M1/0648 ,  H03M1/662 ,  H03M1/68 ,  H03M1/747

Abstract: A digital to analog converter (DAC) includes a thermometer coder that generates a plurality of micro-current source analog controls on a frame-by-frame or symbol-by-symbol basis and to process digital inputs from symbols or frames of data based on a thermometer coding to generate a plurality of micro-current source inputs. A plurality of micro-current sources generate a corresponding plurality of micro-current source outputs in response to the plurality of micro-current source inputs, wherein first selected ones of the plurality of micro-current sources are powered-off in response to the plurality of micro-current source analog controls for a first symbol or frame of the plurality of symbols or frames of data. A summing circuit generates an analog output based a sum of the corresponding plurality of micro-current source outputs.

公开(公告)号：US20120280845A1

公开(公告)日：2012-11-08

申请号：US13099797

申请日：2011-05-03

Applicant: Honglei Wu ,  Mengchang Doong

Inventor： Honglei Wu ,  Mengchang Doong

IPC: H03M1/66

CPC classification number: H03M1/0648 ,  H03M1/685

Abstract: A digital-to-analog converter (DAC) uses thermometer coding over a certain code range. A switch array for the certain code range is implemented into a smaller area of the integrated circuit die so as to take advantage of the lower gradient inherent in the smaller area. By implementing the certain input code range into the smaller switch array area, further improved linearity in that input code range is achieved at the expense of worse linearity in the other input code ranges, but without increasing power consumption and/or chip-area of the integrated circuit die.

Abstract translation: 数模转换器（DAC）在某个代码范围内使用温度计编码。 用于特定代码范围的开关阵列被实现到集成电路管芯的较小区域中，以便利用较小区域中固有的较低梯度的优点。 通过将某些输入代码范围实现到较小的开关阵列区域中，在输入代码范围内进一步提高的线性度以牺牲其他输入代码范围内更差的线性度为代价，但不增加功耗和/或芯片面积 集成电路管芯。

公开(公告)号：US06954164B2

公开(公告)日：2005-10-11

申请号：US10680478

申请日：2003-10-07

Applicant: Kwang-Hee Lee ,  Kyeong-Tae Moon

Inventor： Kwang-Hee Lee ,  Kyeong-Tae Moon

IPC: H01L21/822 ,  G06F17/50 ,  H01L27/04 ,  H01L27/10 ,  H01L29/739 ,  H03M1/06 ,  H03M1/66 ,  H03M1/68 ,  H03M1/74

CPC classification number: H03M1/0648 ,  H03M1/682 ,  H03M1/747

Abstract: The present invention discloses a transistor array and a layout method, the array including a plurality of first LSB transistors arranged along diagonal directions of a central portion of a first quadrant of an array including a plurality of rows and a plurality of columns; a plurality of first MSB transistors arranged along diagonal directions above and below the plurality of first LSB transistors, respectively; a plurality of second LSB transistors and a plurality of second MSB transistors arranged on a second quadrant of the array to be symmetrical in a Y-axis direction to the plurality of first LSB transistors and the plurality of first MSB transistors; a plurality of third LSB transistors and a plurality of third MSB transistors arranged on a third quadrant of the array to be symmetrical in an X-axis direction to the plurality of first LSB transistors and the plurality of first MSB transistors; and a plurality of fourth LSB transistors and a plurality of fourth MSB transistors arranged on a fourth quadrant of the array to be symmetrical in a Y-axis direction to the plurality of third LSB transistors and the plurality of third MSB transistors, such that the transitor array can minimize the effects of temperature distribution and process variation.

Abstract translation: 本发明公开了一种晶体管阵列和布局方法，该阵列包括沿着包括多行和多列的阵列的第一象限的中心部分的对角线布置的多个第一LSB晶体管; 分别沿着多个第一LSB晶体管的上下方向排列的多个第一MSB晶体管; 多个第二LSB晶体管和多个第二MSB晶体管，其布置在所述阵列的第二象限上，以在Y轴方向上与所述多个第一LSB晶体管和所述多个第一MSB晶体管对称; 多个第三LSB晶体管和多个第三MSB晶体管，其布置在阵列的第三象限上，以在X轴方向上与多个第一LSB晶体管和多个第一MSB晶体管对称; 以及布置在所述阵列的第四象限上的多个第四LSB晶体管和多个第四MSB晶体管，以在Y轴方向上与所述多个第三LSB晶体管和所述多个第三MSB晶体管对称，使得所述过渡电极 阵列可以最小化温度分布和工艺变化的影响。

公开(公告)号：US06720898B1

公开(公告)日：2004-04-13

申请号：US10410746

申请日：2003-04-10

Applicant: Geir Sigurd Ostrem

Inventor： Geir Sigurd Ostrem

IPC: H03M166

CPC classification number: H03M1/0648 ,  H03M1/747

Abstract: Current source arrays having a plurality of current sources arranged in an array of columns and rows are disclosed. The outputs of the current sources in even rows of the first column of an array are connected to the output of a current source in each of the other columns located along a first diagonal through the array from the respective current source in the first column. Also the outputs of the current sources in odd rows of the first column of the array are each connected to the output of a current source in each of the other columns located along a second diagonal through the array from the respective current source in the first column, the second diagonals being in an opposite diagonal direction from the first diagonals. When used in a current steering thermometer DAC, preferably but not necessarily, the current sources for the least significant bits are located on a main diagonal of the array.

Abstract translation: 公开了具有排列成列和行阵列的多个电流源的电流源阵列。 阵列的第一列的偶数行中的电流源的输出连接到沿着第一对角线的每个其他列中的电流源的输出，该第一对角线通过来自第一列中的相应电流源的阵列。 此外，阵列的第一列的奇数行中的电流源的输出各自连接到沿着第一对角线的第二对角线中的每一个中的电流源的输出，该第二对角线通过阵列从第一列中的相应电流源 第二对角线与第一对角线处于相对的对角线方向。 当在当前的转向温度计DAC中使用时，优选地但不是必须地，用于最低有效位的电流源位于阵列的主对角线上。

公开(公告)号：US06507272B1

公开(公告)日：2003-01-14

申请号：US09915464

申请日：2001-07-26

Applicant: Richard Nicholson ,  Simon Churchill ,  Hao Tang

Inventor： Richard Nicholson ,  Simon Churchill ,  Hao Tang

IPC: H01L101

CPC classification number: H03M1/0648 ,  H01L27/0802 ,  H03M1/685 ,  H03M1/765

Abstract: Enhanced linearity, low switching perturbation resistor string matrices. The resistor strings are arranged in an array of a plurality of rows of resistive elements and electrically arranged with rows equally spaced above and below the physical centerline of the array being coupled together in an opposite sense. Preferably also physically adjacent rows are equally spaced from the center of the electrical order of rows. This connection prevents accumulation of errors due to vertical and horizontal resistance gradients over the array. Also node selection by controlling node select transistors coupled to column select lines to select one node in each row, and also controlling row select transistors to select the row of the desired node minimizes settling time after a tap change by inducing equal and opposite voltage changes at points close together along the resistor string, whether in the array of the present invention or in the snake configuration.

Abstract translation: 增强的线性度，低开关扰动电阻串矩阵。 电阻器串被布置成多行电阻元件的阵列，并且电排列成与阵列的物理中心线的上方和下方相等的间隔以相反的意义耦合在一起。 优选地，物理上相邻的行与电排列的中心等距地间隔开。 这种连接可防止阵列上的垂直和水平电阻梯度引起的误差累积。 还通过控制节点选择晶体管来选择耦合到列选择线以选择每行中的一个节点，并且还控制行选择晶体管以选择所需节点的行，通过在抽头变换之后引起相等且相反的电压变化来最小化最小化稳定时间 无论是在本发明的阵列中还是在蛇形结构中，沿着电阻串一起靠近的点。

公开(公告)号：US5021784A

公开(公告)日：1991-06-04

申请号：US547901

申请日：1990-07-02

Applicant: Dirk W. J. Groeneveld ,  Hendrikus J. Schouwenaars

Inventor： Dirk W. J. Groeneveld ,  Hendrikus J. Schouwenaars

IPC: G01R19/25 ,  H03M1/06 ,  H03M1/10 ,  H03M1/74

CPC classification number: H03M1/0648 ,  H03M1/1004

Abstract: A signal source arrangement includes a group of signal sources calibrated so that each signal source produces an identical unit signal. The unit signals are combined to form the output signal. Each signal source also produces a similar undesirable spurious signal caused by the calibration procedure. The combination sequence or the calibration sequence is arranged so as to minimize the undesirable effect of the resulting spurious signals in the combined output signal.

公开(公告)号：US20240348258A1

公开(公告)日：2024-10-17

申请号：US18755317

申请日：2024-06-26

Applicant: Apple Inc.

Inventor： Filipe Tabarani ,  Timo W. Gossmann

IPC: H03M1/00 ,  H03M1/06 ,  H04L27/20 ,  H04L27/36 ,  H03M1/66

CPC classification number: H03M1/002 ,  H03M1/0648 ,  H04L27/206 ,  H04L27/362 ,  H03M1/66

Abstract: The current disclosure is related to a column and line digital-to-analog converter (DAC) with a hybrid coupler for generating quadrature analog signals. The DAC may include an array of unit power amplifiers (cells). A first portion of the cells of the array may be coupled to a first column decoder to receive in-phase components of digital signals and a second portion of the cells may be coupled to a second column decoder to receive quadrature components of the digital signals. The first portion of the cells of the array may generate in-phase components of analog signals and the second portion of the cells of the array may generate quadrature components of the analog signals. A hybrid coupler of the DAC may receive the in-phase and quadrature components of the analog signals with a similar phase, delay the quadrature components by a phase delay (e.g., 90 degrees), and output the resulting analog signals.

公开(公告)号：US20230421167A1

公开(公告)日：2023-12-28

申请号：US17846520

申请日：2022-06-22

Applicant: STMicroelectronics S.r.l.

Inventor： Francesco STILGENBAUER

IPC: H03M1/06

CPC classification number: H03M1/0668 ,  H03M1/0648 ,  H03M1/0626

Abstract: A signal processing circuit includes a filter generating a quantizer input signal from a noise shaping input signal and a quantizer output signal. A quantizer divides the quantizer input signal by a scaling factor to produce a noise shaping output signal and multiplies the noise shaping output signal by the scaling factor to produce the quantizer output signal. Receiver circuitry scales the quantizer output signal by a second scaling factor. A dynamic range optimization circuit compares a current value of the noise shaping input signal to a threshold value, lowers or raises the scaling factor in response to the comparison, and proportionally lowers or raises the scaling factor such that a ratio between the scaling factor and second scaling factor remains substantially constant.