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    Power switch
    21.
    发明授权
    Power switch 有权
    开关;电源开关

    公开(公告)号：US08598938B2

    公开(公告)日：2013-12-03

    申请号：US13666727

    申请日：2012-11-01

    Applicant: STMicroelectronics SA

    Inventor： Philippe Galy ,  Johan Bourgeat

    IPC: H03K17/687

    CPC classification number: H03K17/063 ,  H01L27/0262

    Abstract: A power switch includes first and second MOS transistors in series between first and second nodes. Both the first and second transistors have a gate coupled to its substrate. First and second resistive elements are coupled between the gate of the first transistor and the first node, and between the gate of the second transistor and the second node, respectively. A triac is coupled between the first and second nodes. The gate of the triac is coupled to a third node common to the first and second transistors. A third MOS transistor has a first conduction electrode coupled to the gate of the first transistor and a second conduction electrode coupled to the gate of the second transistor.

    Abstract translation: 电源开关包括在第一和第二节点之间串联的第一和第二MOS晶体管。 第一和第二晶体管都具有耦合到其衬底的栅极。 第一和第二电阻元件分别耦合在第一晶体管的栅极和第一节点之间，以及第二晶体管的栅极和第二节点之间。 三端双向可控硅开关元件耦合在第一和第二节点之间。 三端双向可控硅开关元件的栅极耦合到第一和第二晶体管共同的第三节点。 第三MOS晶体管具有耦合到第一晶体管的栅极的第一导电电极和耦合到第二晶体管的栅极的第二导电电极。

    Bidirectional Semiconductor Device for Protection Against Electrostatic Discharges, Usable on Silicon on Insulator
    22.
    发明申请
    Bidirectional Semiconductor Device for Protection Against Electrostatic Discharges, Usable on Silicon on Insulator 有权
    用于防止静电放电的双向半导体器件，可用于绝缘体上的硅

    公开(公告)号：US20130214326A1

    公开(公告)日：2013-08-22

    申请号：US13768730

    申请日：2013-02-15

    Applicant: STMICROELECTRONICS SA

    Inventor： Philippe Galy ,  Nicolas Guitard ,  Thomas Benoist

    IPC: H01L29/74

    CPC classification number: H01L29/7424 ,  H01L27/0262 ,  H01L29/87

    Abstract: A device includes, within a layer of silicon on insulator, a central semiconductor zone including a central region having a first type of conductivity, two intermediate regions having a second type of conductivity opposite to that of the first one, respectively disposed on either side of and in contact with the central region in order to form two PN junctions, two semiconductor end zones respectively disposed on either side of the central zone, each end zone comprising two end regions of opposite types of conductivity, in contact with the adjacent intermediate region, the two end regions of each end zone being mutually connected electrically in order to form the two terminals of the device.

    Abstract translation: 一种器件包括在绝缘体上的硅层内的包括具有第一类型导电性的中心区域的中心半导体区域，具有与第一类型导电性相反的第二类型导电率的第二类型的中间区域分别设置在 并且与中心区域接触以形成两个PN结，两个半导体端部区域分别设置在中心区域的任一侧上，每个端部区域包括与相邻中间区域接触的相反导电类型的两个端部区域， 每个端部区域的两个端部区域相互电连接以形成装置的两个端子。

    Integrated artificial neuron device
    23.
    发明授权
    Integrated artificial neuron device 有权

    公开(公告)号：US11954589B2

    公开(公告)日：2024-04-09

    申请号：US17572899

    申请日：2022-01-11

    Applicant: STMicroelectronics SA

    Inventor： Philippe Galy ,  Thomas Bedecarrats

    IPC: G06N3/063 ,  G06N3/04 ,  G06N3/049 ,  G06N3/065 ,  G11C11/54 ,  H01L27/02 ,  H01L29/423 ,  H03K3/356

    CPC classification number: G06N3/065 ,  G06N3/049 ,  G06N3/063 ,  G11C11/54 ,  H01L27/027 ,  H01L27/0285 ,  G06N3/04 ,  H01L29/42376 ,  H03K3/356

    Abstract: An artificial-neuron device includes an integration-generation circuit coupled between an input at which an input signal is received and an output at which an output signal is delivered, and a refractory circuit inhibiting the integrator circuit after the delivery of the output signal. The refractory circuit is formed by a first MOS transistor having a first conduction-terminal coupled to a supply node, a second conduction-terminal coupled to a common node, and a control-terminal coupled to the output, and a second MOS transistor having a first conduction-terminal coupled to the input, a second conduction-terminal coupled to a reference node at which a reference voltage is received, and a control-terminal coupled to the common node. A resistive-capacitive circuit is coupled between the supply node and the reference node and having a tap coupled to the common node, with the inhibition duration being dependent upon a time constant of the resistive-capacitive circuit.

    Integrated circuit with double isolation of deep and shallow trench-isolation type
    26.
    发明授权
    Integrated circuit with double isolation of deep and shallow trench-isolation type 有权

    公开(公告)号：US11450689B2

    公开(公告)日：2022-09-20

    申请号：US16927510

    申请日：2020-07-13

    Applicant: STMicroelectronics SA

    Inventor： Thomas Bedecarrats ,  Philippe Galy

    IPC: H01L27/12

    Abstract: A silicon-on-insulator semiconductor substrate supports rows extending in a direction. Each row includes complementary MOS transistors and associated contact regions allowing back gate of the complementary MOS transistors to be biased. All transistors and associated contact regions of a given row are mutually isolated by a first trench isolation. Each row is bordered on opposed edges extending parallel to said direction by corresponding second trench isolations that are shallower than the first trench isolation.

    BiMOS transistor
    27.
    发明授权
    BiMOS transistor 有权

    公开(公告)号：US11387354B2

    公开(公告)日：2022-07-12

    申请号：US16870116

    申请日：2020-05-08

    Applicant: STMicroelectronics SA

    Inventor： Philippe Galy ,  Louise De Conti

    IPC: H01L29/739 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

    Abstract: A BiMOS-type transistor includes a gate region, a channel under the gate region, a first channel contact region and a second channel contact region. The first channel contact region is electrically coupled to the gate region to receive a first potential. The second channel contact region is electrically coupled to receive a second potential.

    Transistor structure
    28.
    发明授权
    Transistor structure 有权

    公开(公告)号：US11380766B2

    公开(公告)日：2022-07-05

    申请号：US16434920

    申请日：2019-06-07

    Applicant: STMicroelectronics SA

    Inventor： Sotirios Athanasiou ,  Philippe Galy

    IPC: H01L29/36 ,  H01L29/786 ,  H01L29/72 ,  H01L29/423 ,  H01L29/10 ,  H01L29/735

    Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.

    DEVICE FOR GENERATING A RANDOM SIGNAL
    30.
    发明申请
    DEVICE FOR GENERATING A RANDOM SIGNAL 审中-公开

    公开(公告)号：US20190114145A1

    公开(公告)日：2019-04-18

    申请号：US16157464

    申请日：2018-10-11

    Applicant: STMicroelectronics SA

    Inventor： Philippe Galy ,  Thomas Bedecarrats

    IPC: G06F7/58 ,  H03K3/84 ,  H03K3/012

    Abstract: An integrated device, for generating a random signal, includes: a first terminal; a pulse signal generator configured to generate a current pulse train on the first terminal; and a first control circuit coupled to the first terminal and configured to convert the current pulse train into a voltage signal randomly including voltage pulses greater than a threshold, the random signal containing the voltage pulses greater than the threshold.

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