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公开(公告)号：US11474546B2
公开(公告)日：2022-10-18
申请号：US17012478
申请日：2020-09-04
Applicant: STMicroelectronics International N.V.
Inventor： Kapil Kumar Tyagi , Nitin Gupta
Abstract: A method is for operating an electronic device formed by a low dropout regulator (LDO) having an output coupled to a first conduction terminal of a transistor, with a second conduction terminal of the transistor being coupled to an output node. The electronic device is turned on by turning on the LDO, removing a DC bias from the second conduction terminal of the transistor by opening a first switch that selectively couples the second conduction terminal of the transistor to a supply node through a first diode coupled transistor and by opening a second switch that selectively couples the second conduction terminal of the transistor to a ground node through a second diode coupled transistor, and turning on the transistor. The electronic device is turned off by turning off the transistor, forming the DC bias at the second conduction terminal of the transistor, and turning off the LDO.
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公开(公告)号：US11171619B2
公开(公告)日：2021-11-09
申请号：US16829088
申请日：2020-03-25
Applicant: STMicroelectronics International N.V.
Inventor： Nitin Gupta , Prashutosh Gupta
Abstract: A differential pair of transistors receives input voltages. Current mirror transistors and cascode transistors are coupled to the differential pair of transistors. The differential pair of transistors is coupled between the cascode transistors and a tail transistor that draws a first bias current from a tail node, the first bias current having a magnitude equal to a product of a total bias current and a constant that is less than one. A first current source transistor draws a second bias current from a node between the differential pair and cascode transistors so the second bias current bypasses one transistor of the differential pair of transistors. The second bias current has a magnitude equal to a product of the total bias current and a value equal to one minus the constant. An output stage is biased by an output at node between the cascode transistors and the current mirror transistors.
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23.发明授权公开(公告)号：US11095297B2
公开(公告)日：2021-08-17
申请号：US16895092
申请日：2020-06-08
Applicant: STMicroelectronics International N.V.
Inventor： Nitin Gupta , Sagnik Mukherjee
Abstract: A voltage controlled oscillator (VCO) circuit generates an output signal having a frequency which is dependent on a control voltage. A current is generated which is itself dependent on an amplitude of the VCO circuit. The generated current accordingly tracks, to an extent, the temperature behavior of the oscillator within the VCO circuit. The oscillator is driven by the sum of the generated current and a control current dependent on the control voltage. The control voltage may, for example, be generated by a phase lock loop (PLL).
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公开(公告)号：US09564904B2
公开(公告)日：2017-02-07
申请号：US14691738
申请日：2015-04-21
Applicant: STMicroelectronics International N.V.
Inventor： Jeet Narayan Tiwari , Nitin Gupta
CPC classification number: H03K21/026 , H03K21/00 , H03K23/00 , H03K23/58 , H03K23/667 , H03K23/68
Abstract: A method of dividing a clock signal by an input signal of N bits with M most significant bits is described herein. The method includes dividing the clock signal by the most significant bits of the input signal 2N-M−1 times out of 2N-M divisions of the clock signal, using a divider. The clock signal is divided by a sum of the most significant bits and the least significant bits one time out of 2N-M divisions of the clock signal, using the divider. The clock signal is also divided by 2N-M, 2N-M times, using the divider.
Abstract translation: 本文描述了将时钟信号除以具有M个最高有效位的N位的输入信号的方法。 该方法包括使用分频器将时钟信号除以时钟信号的2N-M分频之外的输入信号2N-M-1的最高有效位。 使用分频器，将时钟信号除以时钟信号的2N-M分频之外的最高有效位和最低有效位之和。 使用分频器也可以将时钟信号除以2N-M，2N-M次。
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公开(公告)号：US20160006442A1
公开(公告)日：2016-01-07
申请号：US14323794
申请日：2014-07-03
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Abhirup Lahiri , Nitin Gupta
Abstract: According to an embodiment, a circuit includes a first charge pump configured to generate a first current at a first node, a second charge pump configured to generate a second current at a second node, a loop filter coupled between the first and second nodes, the loop filter including a first filter path coupled to the first node, a second filter path coupled to the second node, and an isolation buffer interposed between the first and second filter paths. The second current at the second node is different than the first current at the first node. The circuit further includes an oscillator configured to apply a first gain to an output of the first filter path and a second gain to an output of the second filter path.
Abstract translation: 根据实施例，电路包括被配置为在第一节点处产生第一电流的第一电荷泵，被配置为在第二节点处产生第二电流的第二电荷泵，耦合在第一和第二节点之间的环路滤波器， 环路滤波器，包括耦合到第一节点的第一滤波器路径，耦合到第二节点的第二滤波器路径以及插在第一和第二滤波器路径之间的隔离缓冲器。 第二节点处的第二个电流与第一节点处的第一个电流不同。 该电路还包括一个振荡器，被配置为对第一滤波器路径的输出施加第一增益，并将第二增益应用于第二滤波器路径的输出。
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Patent Agency Ranking
公开(公告)号：US08933737B1
公开(公告)日：2015-01-13
申请号：US14046041
申请日：2013-10-04
Inventor： Kallol Chatterjee , Nitin Agarwal , Junaid Yousuf , Nitin Gupta , Pierre Dautriche
CPC classification number: H03L7/095
Abstract: A variable frequency clock generator. In aspects, a clock generator includes a droop detector circuit configured to monitor a voltage supply to an integrated circuit. If the supply voltage falls below a specific threshold, a droop voltage flag may be set such that a frequency-locked loop is triggered into a droop voltage mode for handling the voltage droop at the supply voltage. In response, a current control signal that is input to an oscillator that generates a system clock signal is reduced by sinking current away from the current control signal to the oscillator. This results in an immediate reduction on the system clock frequency. Such a state remains until the voltage droop has dissipated when the current path is removed for sinking some of the current.
Abstract translation: 变频时钟发生器。 在方面中，时钟发生器包括下垂检测器电路，其被配置为监视对集成电路的电压供应。 如果电源电压低于特定阈值，则可以设置下降电压标志，使得频率锁定环路被触发到用于处理电源电压的电压下降的下降电压模式。 作为响应，通过将电流从电流控制信号吸收到振荡器来减小输入到产生系统时钟信号的振荡器的电流控制信号。 这将立即降低系统时钟频率。 当去除电流路径以吸收一些电流时，这种状态保持直到电压下降消散。
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公开(公告)号：US11016519B2
公开(公告)日：2021-05-25
申请号：US16694028
申请日：2019-11-25
Applicant: STMicroelectronics International N.V.
Inventor： Ankit Gupta , Nitin Gupta , Prashutosh Gupta
Abstract: A voltage regulator includes an error amplifier producing an error voltage from a reference voltage and a feedback voltage. A voltage-to-current converter converts the error voltage to an output current, and a feedback resistance generates the feedback voltage from the output current. The error amplifier includes a differential pair of transistors receiving the feedback voltage and the reference voltage, a first pair of transistors operating in saturation and coupled to the differential pair of transistors at an output node and a bias node, a second pair of transistors operating in a linear region and coupled to the first pair of transistors at a pair of intermediate nodes. A compensation capacitor is coupled to one of the pair of intermediate nodes so as to compensate the error amplifier for a parasitic capacitance. An output at the output node is a function of a difference between the reference voltage and feedback voltage.
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公开(公告)号：US10911053B2
公开(公告)日：2021-02-02
申请号：US15966134
申请日：2018-04-30
Applicant: STMicroelectronics International N.V.
Inventor： Nitin Gupta , Kapil Kumar Tyagi
Abstract: A PLL includes a phase frequency detector (PFD) receiving an input signal and feedback signal, and producing a control signal. A charge pump receives the control signal and produces an initial VCO control. A loop filter generates a fine VCO control and intermediate output based upon the initial VCO control. A coarse control circuit includes an integrator having a first input receiving the intermediate output, a second input, and generating a coarse VCO control, a first switch coupling a reference voltage to the second input, a buffer buffering output of the integrator, and a second switch coupling output of the integrator to the second input of the integrator. A VCO receives the fine VCO control and the coarse VCO control, and generates an output signal having a frequency based thereupon. A feedback path receives the output signal and produces the feedback signal.
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公开(公告)号：US10177773B2
公开(公告)日：2019-01-08
申请号：US15297537
申请日：2016-10-19
Applicant: STMicroelectronics International N.V.
Inventor： Nitin Gupta , Jeet Narayan Tiwari
Abstract: In accordance with an embodiment, a circuit includes an input clock terminal, an output clock terminal, a first input data terminal, and a set of input data terminals having a number of terminals. A divide-by-two block is coupled to the output clock terminal. A modular one-shot clock divider is coupled between the input clock terminal and the divide-by-two block. The modular one-shot clock divider is further coupled to the set of input data terminals. An intermediate clock generation block is coupled between the input clock terminal and the modular one-shot clock divider. The intermediate clock generation block includes a first digital logic block coupled between the input clock terminal and the modular one-shot clock divider. The first digital logic block is further coupled to the first input data terminal, and a clock-blocking block is coupled between the divide-by-two block and the first digital logic block.
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公开(公告)号：US20180284822A1
公开(公告)日：2018-10-04
申请号：US15475266
申请日：2017-03-31
Applicant: STMicroelectronics International N.V.
Inventor： Kapil Kumar Tyagi , Nitin Gupta
IPC: G05F1/575
Abstract: A low dropout regulator produces output at an intermediate node. A resistive divider is coupled between the intermediate node and ground and provides a feedback signal to the low dropout regulator. A transistor has a first conduction terminal coupled to the intermediate node and a second conduction terminal coupled to an output node. A first impedance is coupled to the output node, a first switch selectively couples the first impedance to a supply node, a second impedance coupled to the output node, and a second switch selectively couples the second impedance to a ground node. Control circuitry is coupled to the control terminal of the transistor and to control terminals of the first and second switches. The control circuitry switches the electronic device to a power down mode by turning off transistor, closing the first and second switches, and turning off the low dropout regulator.
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