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1.发明申请公开(公告)号：US20190288693A1
公开(公告)日：2019-09-19
申请号：US15924584
申请日：2018-03-19
Applicant: STMicroelectronics International N.V.
Inventor： Nitin Gupta , Jeet Narayan Tiwari
Abstract: Disclosed is a method of locking a locked loop quickly, including receiving an input signal having an input frequency, and generating an intermediate signal having an intermediate frequency intended to be equal to a geometric mean of the input frequency and a desired frequency, but not equal. Results of division of the desired output frequency by the intermediate frequency are estimated, producing a first divider value. A first locked loop utilizing a controllable oscillator is activated. A divider value of the first locked loop is set to the first divider value, and the intermediate signal is provided to the first locked loop, so that when the first locked loop reaches lock, the controllable oscillator produces the desired frequency. When the first locked loop reaches lock, a second locked loop that utilizes the controllable oscillator is activated, the first locked loop is deactivated, and generation of the intermediate signal is ceased.
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公开(公告)号：US20180109266A1
公开(公告)日：2018-04-19
申请号：US15297537
申请日：2016-10-19
Applicant: STMicroelectronics International N.V.
Inventor： Nitin Gupta , Jeet Narayan Tiwari
CPC classification number: H03L7/1974 , H03K19/20 , H03K21/00 , H03K21/10 , H03K23/00 , H03K23/667 , H03K23/68 , H03K23/70
Abstract: In accordance with an embodiment, a circuit includes an input clock terminal, an output clock terminal, a first input data terminal, and a set of input data terminals having a number of terminals. A divide-by-two block is coupled to the output clock terminal. A modular one-shot clock divider is coupled between the input clock terminal and the divide-by-two block. The modular one-shot clock divider is further coupled to the set of input data terminals. An intermediate clock generation block is coupled between the input clock terminal and the modular one-shot clock divider. The intermediate clock generation block includes a first digital logic block coupled between the input clock terminal and the modular one-shot clock divider. The first digital logic block is further coupled to the first input data terminal, and a clock-blocking block is coupled between the divide-by-two block and the first digital logic block.
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公开(公告)号：US09564904B2
公开(公告)日：2017-02-07
申请号：US14691738
申请日：2015-04-21
Applicant: STMicroelectronics International N.V.
Inventor： Jeet Narayan Tiwari , Nitin Gupta
CPC classification number: H03K21/026 , H03K21/00 , H03K23/00 , H03K23/58 , H03K23/667 , H03K23/68
Abstract: A method of dividing a clock signal by an input signal of N bits with M most significant bits is described herein. The method includes dividing the clock signal by the most significant bits of the input signal 2N-M−1 times out of 2N-M divisions of the clock signal, using a divider. The clock signal is divided by a sum of the most significant bits and the least significant bits one time out of 2N-M divisions of the clock signal, using the divider. The clock signal is also divided by 2N-M, 2N-M times, using the divider.
Abstract translation: 本文描述了将时钟信号除以具有M个最高有效位的N位的输入信号的方法。 该方法包括使用分频器将时钟信号除以时钟信号的2N-M分频之外的输入信号2N-M-1的最高有效位。 使用分频器，将时钟信号除以时钟信号的2N-M分频之外的最高有效位和最低有效位之和。 使用分频器也可以将时钟信号除以2N-M，2N-M次。
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公开(公告)号：US11921537B2
公开(公告)日：2024-03-05
申请号：US17821398
申请日：2022-08-22
Applicant: STMicroelectronics International N.V.
Inventor： Ankur Bal , Jeet Narayan Tiwari
Abstract: An integrated circuit includes a first circuit block operating with a first clock signal and a second circuit block operating with a second clock signal. The first circuit block includes a clock phase generator that receives the first clock signal and outputs a plurality of phase signals. The first circuit block includes a phase selector that receives the phase signals and the second clock signal and selects one of the phase signals based on the second clock signal. The first circuit block transmits data to the second circuit block based on the selected phase signal.
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Patent Agency Ranking
5.发明授权公开(公告)号：US10566980B2
公开(公告)日：2020-02-18
申请号：US15924584
申请日：2018-03-19
Applicant: STMicroelectronics International N.V.
Inventor： Nitin Gupta , Jeet Narayan Tiwari
Abstract: Disclosed is a method of locking a locked loop quickly, including receiving an input signal having an input frequency, and generating an intermediate signal having an intermediate frequency intended to be equal to a geometric mean of the input frequency and a desired frequency, but not equal. Results of division of the desired output frequency by the intermediate frequency are estimated, producing a first divider value. A first locked loop utilizing a controllable oscillator is activated. A divider value of the first locked loop is set to the first divider value, and the intermediate signal is provided to the first locked loop, so that when the first locked loop reaches lock, the controllable oscillator produces the desired frequency. When the first locked loop reaches lock, a second locked loop that utilizes the controllable oscillator is activated, the first locked loop is deactivated, and generation of the intermediate signal is ceased.
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公开(公告)号：US20160315621A1
公开(公告)日：2016-10-27
申请号：US14691738
申请日：2015-04-21
Applicant: STMicroelectronics International N.V.
Inventor： Jeet Narayan Tiwari , Nitin Gupta
IPC: H03K21/02
CPC classification number: H03K21/026 , H03K21/00 , H03K23/00 , H03K23/58 , H03K23/667 , H03K23/68
Abstract: A method of dividing a clock signal by an input signal of N bits with M most significant bits is described herein. The method includes dividing the clock signal by the most significant bits of the input signal 2N-M−1 times out of 2N-M divisions of the clock signal, using a divider. The clock signal is divided by a sum of the most significant bits and the least significant bits one time out of 2N-M divisions of the clock signal, using the divider. The clock signal is also divided by 2N-M, 2N-M times, using the divider.
Abstract translation: 本文描述了将时钟信号除以具有M个最高有效位的N位的输入信号的方法。 该方法包括使用分频器将时钟信号除以时钟信号的2N-M分频之外的输入信号2N-M-1的最高有效位。 使用分频器，将时钟信号除以时钟信号的2N-M分频之外的最高有效位和最低有效位之和。 使用分频器也可以将时钟信号除以2N-M，2N-M次。
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公开(公告)号：US11251784B2
公开(公告)日：2022-02-15
申请号：US17193532
申请日：2021-03-05
Applicant: STMicroelectronics International N.V.
Inventor： Jeet Narayan Tiwari , Anand Kumar , Prashutosh Gupta
Abstract: A divider circuit includes a subtract-by-two circuit receiving MSBs of an input and producing a subtracted-by-two output, a subtract-by-one circuit receiving the MSBs and producing a subtracted-by-one output, a first multiplexer passing the subtracted-by-two or the subtracted-by-one output based on a first control signal, a second multiplexer passing output of the first multiplexer or the MSBs based on a second control signal to produce an asynchronous divisor. An asynchronous one-shot N+2 divider divides an input clock by the asynchronous divisor to produce a first divided signal. An output flip-flop receives the first divided signal and is clocked by an inverse of the input clock to produce a second divided signal. A third multiplexer passes the first divided signal or the second divided signal in response to a select load signal to produce a multiplexer output. A divider divides the multiplexer output by a set divisor to produce an output clock.
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公开(公告)号：US10944387B2
公开(公告)日：2021-03-09
申请号：US16896463
申请日：2020-06-09
Applicant: STMicroelectronics International N.V.
Inventor： Ankur Bal , Jeet Narayan Tiwari
IPC: H03K5/133 , H03K5/1534 , H03K3/027 , H03K21/08 , H03K5/00
Abstract: A delay line includes a delay chain, a pulse generator generating a pulse based on a received input signal, and a delay chain control circuit. The delay chain control circuit has a first input receiving the pulse, a second input receiving output from a last element of the delay chain, and a selection input receiving a delayed version of the received input signal. The delay chain control circuit has an output coupled to provide input to a first element of the delay chain in response to the delayed version of the received input signal. An output selection circuit receives outputs from each element of the delay chain, counts assertions of the output of the last element of the delay chain and, in response to the count being equal to a desired count, passes a desired one of the outputs of the elements of the delay chain as output.
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公开(公告)号：US10177773B2
公开(公告)日：2019-01-08
申请号：US15297537
申请日：2016-10-19
Applicant: STMicroelectronics International N.V.
Inventor： Nitin Gupta , Jeet Narayan Tiwari
Abstract: In accordance with an embodiment, a circuit includes an input clock terminal, an output clock terminal, a first input data terminal, and a set of input data terminals having a number of terminals. A divide-by-two block is coupled to the output clock terminal. A modular one-shot clock divider is coupled between the input clock terminal and the divide-by-two block. The modular one-shot clock divider is further coupled to the set of input data terminals. An intermediate clock generation block is coupled between the input clock terminal and the modular one-shot clock divider. The intermediate clock generation block includes a first digital logic block coupled between the input clock terminal and the modular one-shot clock divider. The first digital logic block is further coupled to the first input data terminal, and a clock-blocking block is coupled between the divide-by-two block and the first digital logic block.
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