公开(公告)号：US12066621B2

公开(公告)日：2024-08-20

申请号：US17720506

申请日：2022-04-14

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto Carminati ,  Nicolo' Boni ,  Andrea Barbieri ,  Marco Zamprogno ,  Luca Molinari

IPC: G02B26/08 ,  H02N2/02 ,  H02N2/06

CPC classification number: G02B26/0858 ,  H02N2/028 ,  H02N2/062

Abstract: A MEMS device includes a semiconductor body with a cavity and forming an anchor portion, a tiltable structure elastically suspended over the cavity, first and second support arms to support the tiltable structure, and first and second piezoelectric actuation structures biasable to deform mechanically, generating a rotation of the tiltable structure around a rotation axis. The piezoelectric actuation structures carry first and second piezoelectric displacement sensors. When the tiltable structure rotates around the rotation axis, the displacement sensors are subject to respective mechanical deformations and generate respective sensing signals in phase opposition to each other, indicative of the rotation of the tiltable structure. The sensing signals are configured to be acquired in a differential manner.

公开(公告)号：US20200233009A1

公开(公告)日：2020-07-23

申请号：US16738459

申请日：2020-01-09

Applicant: STMicroelectronics S.r.l.

Inventor： Marco Zamprogno

IPC: G01P15/12 ,  H03M1/00

Abstract: A circuit configured to sense an input analog signal generated by a sensor at a first frequency and to generate an output digital signal indicative of the sensed input analog signal. The circuit includes a conditioning circuit, an ADC, a feedback circuit, and a low-pass filter. The conditioning circuit is configured to receive the input analog signal and to generate a conditioned analog signal. The ADC is configured to provide a converted digital signal based on the conditioned analog signal. The feedback circuit includes a band-pass filter configured to selectively detect a periodic signal at a second frequency higher than the first frequency and to act on the conditioning circuit to counter variations of the periodic signal at the second frequency. The low-pass filter is configured to filter out the periodic signal from the converted digital signal to generate the output digital signal.

公开(公告)号：US10541692B1

公开(公告)日：2020-01-21

申请号：US16455222

申请日：2019-06-27

Applicant: STMicroelectronics S.r.l. ,  Politecnico Di Milano

Inventor： Marco Zamprogno ,  Alireza Tajfar

IPC: H03L7/08 ,  H03L7/081 ,  H03L7/089 ,  H03K5/134 ,  H03K5/00

Abstract: A delay locked loop includes a control loop receiving reference and feedback clock signals, and generating biasing voltages therefrom. A delay chain receives the reference clock signal and generates N successively delayed versions thereof, each at a successive tap thereof. The Nth delayed version is the feedback clock signal. The control loop has a phase detector asserting an up signal when a phase of the feedback clock signal lags that of the reference clock signal, asserting a down signal when the phase of the feedback clock signal leads that of the reference clock signal. A digital filtering block compares a number of assertions of the up signal during the period of the reference clock signal to those of the down signal, and asserts an up or down command signal based thereupon. A biasing voltage generation circuit receives the up and down command signals and generates the biasing voltages therefrom.