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公开(公告)号：US11387625B2
公开(公告)日：2022-07-12
申请号：US16455063
申请日：2019-06-27
Applicant: STMicroelectronics S.r.l. , Politecnico Di Milano
Inventor： Marco Zamprogno , Alireza Tajfar
Abstract: A pulsed signal generator generates a pulsed signal having a pulse width intended to be equal to a given fraction of a pulse width of a reference clock. A reference current source outputs current having a reference magnitude, and a comparison current source outputs current having a magnitude that is a function of the reference magnitude and the given fraction. A comparison circuit compares a total current output by one of the reference current source and the comparison current source during pulses of the reference clock to a total current output by the other of the reference current source and the comparison current source during pulses of the pulsed signal equal in number to the pulses of the reference clock in order to determine whether the pulse width of the pulse signal is less than or equal to the given fraction of the pulse width of the reference clock.
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公开(公告)号：US10826268B1
公开(公告)日：2020-11-03
申请号：US16454717
申请日：2019-06-27
Applicant: STMicroelectronics S.r.l. , Politecnico Di Milano
Inventor： Marco Zamprogno , Alireza Tajfar
Abstract: A circuit includes a capacitance coupled between a high voltage node and ground, a laser diode having an anode coupled to the high voltage node and a cathode coupled to an output node, and a current source coupled between the output node and ground. The current source turns on based on assertion of a trigger signal and sinks current from the capacitance to ground to thereby cause the laser diode to lase, and turns off based on deassertion of the trigger signal. A clamping circuit is coupled between the output node and the high voltage node, and clamps voltage at the output node occurring when the current source switches off.
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公开(公告)号：US10541692B1
公开(公告)日：2020-01-21
申请号：US16455222
申请日：2019-06-27
Applicant: STMicroelectronics S.r.l. , Politecnico Di Milano
Inventor： Marco Zamprogno , Alireza Tajfar
Abstract: A delay locked loop includes a control loop receiving reference and feedback clock signals, and generating biasing voltages therefrom. A delay chain receives the reference clock signal and generates N successively delayed versions thereof, each at a successive tap thereof. The Nth delayed version is the feedback clock signal. The control loop has a phase detector asserting an up signal when a phase of the feedback clock signal lags that of the reference clock signal, asserting a down signal when the phase of the feedback clock signal leads that of the reference clock signal. A digital filtering block compares a number of assertions of the up signal during the period of the reference clock signal to those of the down signal, and asserts an up or down command signal based thereupon. A biasing voltage generation circuit receives the up and down command signals and generates the biasing voltages therefrom.
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公开(公告)号：US11057022B2
公开(公告)日：2021-07-06
申请号：US16454872
申请日：2019-06-27
Applicant: STMicroelectronics S.r.l. , Politecnico Di Milano
Inventor： Marco Zamprogno , Alireza Tajfar
Abstract: A monostable circuit includes a delay cell with a reference generator generating a reference current based upon a PVT invariant resistance and a threshold voltage, and a delay block with an output capacitor and an output circuit altering an amount of charge stored on the output capacitor as a function of the reference current, in response to an input signal. An inverter has an input coupled to the output circuit. A logic circuit logically combines output of the inverter and the input signal to generate a monostable trigger pulse. The output circuit includes a current source sourcing the reference current to the output capacitor in response to a first logic state of an input signal, and a current sink sinking current from the output capacitor to discharge the output capacitor, in response to a second logic state of the input signal.
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公开(公告)号：US11418007B2
公开(公告)日：2022-08-16
申请号：US17026495
申请日：2020-09-21
Applicant: STMicroelectronics S.r.l. , Politecnico Di Milano
Inventor： Marco Zamprogno , Alireza Tajfar
Abstract: A level-shifter includes an input node coupled to a laser driver input receiving a trigger signal, the input node receiving a signal indicating generation of a laser drive-pulse. A p-channel transistor has a source coupled to a supply node, a drain coupled to an output node, and a gate coupled to the input node. An n-channel transistor has a drain coupled to the drain of the p-channel transistor, a source coupled to ground, and a gate coupled to the input node. A first switch couples the input node to the output node. Another p-channel transistor has a source coupled to the supply node, a drain coupled to the output node by a second switch, and a gate coupled to the input node. The first switch closes and second switch opens when the signal is low, and the first switch opens and second switch closes when the signal is high.
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Patent Agency Ranking
公开(公告)号：US12015346B2
公开(公告)日：2024-06-18
申请号：US17565674
申请日：2021-12-30
Applicant: STMicroelectronics S.r.l.
Inventor： Andrea Barbieri , Aldo Vidoni , Marco Zamprogno
CPC classification number: H02M3/158 , H02M1/0025 , H02M1/08
Abstract: A DC-DC boost converter includes an inductor coupled between an input voltage and an input node, a diode coupled between the input node and an output node, and an output capacitor coupled between the output node and ground such that an output voltage is formed across the output capacitor. A switch selectively couples the input node to ground in response to a drive signal. Control loop circuitry includes an error amplifier to generate an analog error voltage based upon a comparison of a feedback voltage to a reference voltage, the feedback voltage being indicative of the output voltage, a quantizer to quantize the analog error voltage to produce a digital error signal, and a drive voltage generation circuit to generate the drive signal as having a duty cycle based upon the digital error signal.
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公开(公告)号：US20180131342A1
公开(公告)日：2018-05-10
申请号：US15587579
申请日：2017-05-05
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Zamprogno , Maurizio Bongiorni , Pasquale Flora
CPC classification number: H03G3/30 , H02J7/0063 , H02J7/345 , H03F3/087 , H03F3/45475 , H03F3/45973 , H03F3/45977 , H03F2203/45021 , H03F2203/45114 , H03F2203/45116 , H03F2203/45212 , H03F2203/45288 , H03F2203/45528 , H03F2203/45536 , H04B10/6933
Abstract: A transimpedance amplifier circuit includes a feedback control loop that generates a compensation current at an input of a transimpedance amplifier. The feedback control loop includes a differential integrator with an integration capacitor. A time constant associated with charging the integration capacitor is variable as a function of a pre-charge control signal. During a pre-charge phase, the pre-charge control signal is set to a first value so as to set the time constant associated with charging the integration capacitor to a first time constant value. During an operation phase, the pre-charge control signal is set to a second value so as to increase the time constant associated with charging the integration capacitor to a second time constant value greater than the first time constant value for the pre-charge phase.
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公开(公告)号：US11422044B2
公开(公告)日：2022-08-23
申请号：US16877746
申请日：2020-05-19
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Zamprogno , Andrea Barbieri , Pasquale Flora , Raffaele Enrico Furceri
Abstract: A bridge driver circuit applies a bias voltage across first and second input nodes of a resistive bridge circuit configured to measure a physical property such as pressure or movement. A sensing circuit senses drive current, bias current and common mode current for the bridge driver and sums the sensed currents to generate a source current. The source current is processed to determine a normalized resistance and temperature of the resistive bridge circuit and from which a temperature dependent sensitivity of the resistive bridge circuit is determined. A voltage output at first and second output nodes of the resistive bridge circuit is processed to determine a value of the physical property. This processing further involves applying a temperature correction in response to the determined temperature dependent sensitivity.
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公开(公告)号：US10187026B2
公开(公告)日：2019-01-22
申请号：US15587579
申请日：2017-05-05
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Zamprogno , Maurizio Bongiorni , Pasquale Flora
Abstract: A transimpedance amplifier circuit includes a feedback control loop that generates a compensation current at an input of a transimpedance amplifier. The feedback control loop includes a differential integrator with an integration capacitor. A time constant associated with charging the integration capacitor is variable as a function of a pre-charge control signal. During a pre-charge phase, the pre-charge control signal is set to a first value so as to set the time constant associated with charging the integration capacitor to a first time constant value. During an operation phase, the pre-charge control signal is set to a second value so as to increase the time constant associated with charging the integration capacitor to a second time constant value greater than the first time constant value for the pre-charge phase.
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公开(公告)号：US20180342994A1
公开(公告)日：2018-11-29
申请号：US15975505
申请日：2018-05-09
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Zamprogno , Maurizio Bongiorni , Pasquale Flora
IPC: H03F3/45
CPC classification number: H03F3/45273 , H03F1/0205 , H03F3/45183 , H03F3/45188 , H03F3/45192 , H03F3/45632 , H03F2200/513 , H03F2203/45654
Abstract: A single-stage differential operational amplifier including an input stage formed by a pair of input transistors having control terminals connected to a respective first and second input, first conduction terminals coupled to a respective first and second output and second conduction terminals coupled to receive a polarization current. An output stage is formed by a pair of output transistors in diode configuration and having control terminals coupled to a relative first conduction terminal and connected to a respective first and second output, and second conduction terminals connected to a reference line. A coupling stage is interposed between the first conduction terminals of the output transistors and the first and second outputs to define the diode configuration of the output transistors and a gain value of the operational amplifier.
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