公开(公告)号：US06842180B1

公开(公告)日：2005-01-11

申请号：US09665923

申请日：2000-09-20

申请人： Subramaniam Maiyuran ,  Vivek Garg ,  Jagannath Keshava ,  Salvador Palanca

发明人： Subramaniam Maiyuran ,  Vivek Garg ,  Jagannath Keshava ,  Salvador Palanca

IPC分类号： G06F12/08 ,  G06F15/167

CPC分类号： G09G5/001 ,  G06F12/0862 ,  G06F12/0897 ,  G06F2212/6022 ,  G06F2212/6026 ,  G09G5/363 ,  G09G5/39

摘要： An electronic device that has an integrated central processing unit (CPU) including a pre-fetch stride analyzer and an out-of-order engine is provided. The electronic device also has a graphics engine, having graphics memory, that is coupled to the integrated CPU. A main memory that is coupled to a memory controller is provided. The memory controller is also coupled to the CPU and the graphics engine. The device has a host address decoder coupled to the integrated CPU. A front side bus (FSB) is provided that is coupled to the integrated CPU and the host address decoder. Also provided is a plurality of memory components. Accordingly, either the plurality of memory components or the graphics memory can be shared to perform alternate memory functions. Additionally, a method is provided that determines allocation availability between memory components in an integrated computer processing unit. The method also shares an available memory component as a pre-fetch buffer and another available memory component as a victim cache.

摘要翻译： 提供具有集成中央处理单元（CPU）的电子设备，其包括预取步幅分析器和无序引擎。 电子设备还具有连接到集成CPU的具有图形存储器的图形引擎。 提供耦合到存储器控制器的主存储器。 存储器控制器还耦合到CPU和图形引擎。 该设备具有耦合到集成CPU的主机地址解码器。 提供了前置总线（FSB），其耦合到集成CPU和主机地址解码器。 还提供了多个存储器组件。 因此，可以共享多个存储器组件或图形存储器以执行备用存储器功能。 此外，提供了一种确定集成计算机处理单元中的存储器组件之间的分配可用性的方法。 该方法还将可用存储器组件作为预取缓冲区和另一可用存储器组件共享作为受害缓存。

公开(公告)号：US06772291B2

公开(公告)日：2004-08-03

申请号：US10206748

申请日：2002-07-26

申请人： Salvador Palanca ,  Subramaniam Maiyuran

发明人： Salvador Palanca ,  Subramaniam Maiyuran

IPC分类号： G06F1212

CPC分类号： G06F12/0848 ,  G06F12/123

摘要： A method and apparatus for cache replacement in a multiple variable-way associative cache is disclosed. The method according to the present techniques partitions a cache array dynamically based upon requests for memory from an integrated device having a plurality of processors.

摘要翻译： 公开了一种用于多可变方式关联高速缓存中的高速缓存替换的方法和装置。 根据本技术的方法基于来自具有多个处理器的集成设备对存储器的请求而动态地划分高速缓存阵列。

公开(公告)号：US06546462B1

公开(公告)日：2003-04-08

申请号：US09475759

申请日：1999-12-30

申请人： Salvador Palanca ,  Stephen A. Fischer ,  Subramaniam Maiyuran

发明人： Salvador Palanca ,  Stephen A. Fischer ,  Subramaniam Maiyuran

IPC分类号： G06F1200

CPC分类号： G06F12/0811 ,  G06F12/0804

摘要： A system and method for flushing a cache line associated with a linear memory address from all caches in the coherency domain. A cache controller receives a memory address, and determines whether the memory address is stored within the closest cache memory in the coherency domain. If a cache line stores the memory address, it is flushed from the cache. The flush instruction is allocated to a write-combining buffer within the cache controller. The write-combining buffer transmits the information to the bus controller. The bus controller locates instances of the memory address stored within external and intel cache memories within the coherency domain; these instances are flushed. The flush instruction can then be evicted from the write-combining buffer. Control bits may be used to indicate whether a write-combining buffer is allocated to the flush instruction, whether the memory address is stored within the closest cache memory, and whether the flush instruction should be evicted from the write-combining buffer.

摘要翻译： 一种用于从一致性域中的所有高速缓存中刷新与线性存储器地址相关联的高速缓存行的系统和方法。 高速缓存控制器接收存储器地址，并且确定存储器地址是否存储在相干域中最接近的高速缓冲存储器中。 如果缓存行存储内存地址，则从缓存中刷新。 刷新指令被分配给高速缓存控制器内的写入组合缓冲器。 写合成缓冲器将信息发送到总线控制器。 总线控制器定位存储在相干域内的外部和英特尔高速缓存存储器中的存储器地址的实例; 这些实例被刷新。 然后可以从写入组合缓冲器中逐出驱动刷新指令。 控制位可以用于指示是否将写入组合缓冲器分配给闪存指令，存储器地址是否存储在最接近的高速缓冲存储器中，以及是否应该从写入组合缓冲器中驱逐刷新指令。

公开(公告)号：US06526499B2

公开(公告)日：2003-02-25

申请号：US09758486

申请日：2001-01-10

申请人： Salvador Palanca ,  Shekoufeh Qawami ,  Niranjan L. Cooray ,  Angad Narang ,  Subramaniam Maiyuran

发明人： Salvador Palanca ,  Shekoufeh Qawami ,  Niranjan L. Cooray ,  Angad Narang ,  Subramaniam Maiyuran

IPC分类号： G06F930

CPC分类号： G06F9/3857 ,  G06F9/30047 ,  G06F9/3824 ,  G06F9/3834 ,  G06F13/1668

摘要： The present invention discloses a method and apparatus for implementing a senior load instruction type. An instruction requesting a memory reference is decoded. The decoded instruction is then dispatched to a memory ordering unit. The instruction is retired from a load buffer and is executed after retiring.

摘要翻译： 本发明公开了一种实现高级加载指令类型的方法和装置。 解码请求存储器参考的指令。 然后将解码的指令分派到存储器订购单元。 该指令从加载缓冲区中退出，并在退出后执行。

公开(公告)号：US06205520B1

公开(公告)日：2001-03-20

申请号：US09053387

申请日：1998-03-31

申请人： Salvador Palanca ,  Vladimir Pentkovski ,  Steve Tsai ,  Subramaniam Maiyuran

发明人： Salvador Palanca ,  Vladimir Pentkovski ,  Steve Tsai ,  Subramaniam Maiyuran

IPC分类号： G06F1200

CPC分类号： G06F9/3824 ,  G06F9/3842 ,  G06F12/0804 ,  G06F12/0888 ,  G06F12/0897

摘要： A processor is disclosed. The processor includes a decoder to decode instructions and a circuit, in response to a decoded instruction, detects an incoming write back or write through streaming store instruction that misses a cache and allocates a buffer in write combining mode. The circuit, in response to a second decoded instruction, detects either an uncacheable speculative write combining store instruction or a second write back streaming store or write through streaming store instruction that hits the buffer and merges the second decoded instruction with the buffer.

摘要翻译： 公开了一种处理器。 处理器包括解码器，用于对指令和电路进行解码，响应于解码的指令，通过错过高速缓冲存储器的流存储指令检测进入写回或写入，并以写入合并模式分配缓冲器。 响应于第二解码指令，该电路检测不可缓存的推测写入组合存储指令或第二回写流存储器，或通过命中缓冲器的流存储指令进行写入，并将第二解码指令与缓冲器合并。

公开(公告)号：US06223258B1

公开(公告)日：2001-04-24

申请号：US09053528

申请日：1998-03-31

申请人： Salvador Palanca ,  Vladimir Pentkovski ,  Steve Tsai

发明人： Salvador Palanca ,  Vladimir Pentkovski ,  Steve Tsai

IPC分类号： G06F1212

CPC分类号： G06F9/30043 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3832 ,  G06F12/0875 ,  G06F12/0888

摘要： A processor is described. The processor includes a decoder to decode instructions and a circuit, in response to a decoded instruction, to detect an incoming load instruction that misses a cache, allocate a buffer to service the incoming load instruction, and issue a bus request to load the data in the buffer without accessing said cache.

摘要翻译： 描述处理器。 所述处理器包括解码器，用于响应于解码指令来解码指令和电路，以检测错过高速缓存的输入加载指令，分配缓冲器来服务输入加载指令，并发出总线请求以将数据加载到 缓冲区不访问所述缓存。

公开(公告)号：US07136984B2

公开(公告)日：2006-11-14

申请号：US11000054

申请日：2004-12-01

申请人： Subramaniam J. Maiyuran ,  Lyman Moulton ,  Salvador Palanca ,  Satish Damaraju

发明人： Subramaniam J. Maiyuran ,  Lyman Moulton ,  Salvador Palanca ,  Satish Damaraju

IPC分类号： G06F12/00

CPC分类号： G06F12/0864 ,  G06F12/0846 ,  G06F2212/1028 ,  Y02D10/13

摘要： In a processor cache, cache circuits are mapped into one or more logical modules. Each module may be powered down independently of other modules in response to microinstructions processed by the cache. Power control may be applied on a microinstruction-by-microinstruction basis. Because the microinstructions determine which modules are used, power savings may be achieved by powering down those modules that are not used. A cache layout organization may be modified to distribute a limited number of ways across addressable cache banks. By associating fewer than a total number of ways to a bank (for example, one or two ways), the size of memory clusters within the bank may be reduced. The reduction in this size of the memory cluster contributes reduces the power needed for an address decoder to address sets within the bank.

公开(公告)号：US06782455B2

公开(公告)日：2004-08-24

申请号：US10155522

申请日：2002-05-23

申请人： Salvador Palanca ,  Lokpraveen B. Mosur

发明人： Salvador Palanca ,  Lokpraveen B. Mosur

IPC分类号： G06F1200

CPC分类号： G06F12/0859 ,  G06F12/0804

摘要： A cache controller is presented having at least one register. The cache controller is connected to a cache memory, which is connected to the register. The cache controller dynamically selects between a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated based on priority. Also presented is a device having a single request queue and a corresponding single set of buffers. The device dynamically selects between a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated based on priority.

摘要翻译： 呈现具有至少一个寄存器的高速缓存控制器。 高速缓存控制器连接到连接到寄存器的高速缓冲存储器。 高速缓存控制器基于可编程回写条目的最大数量的高速缓存管理方案和基于优先级分配回写条目和传入核心请求的高速缓存管理方案来动态地选择。 还提出了具有单个请求队列和相应的单组缓冲器的设备。 该设备基于最大可编程回写条目数量的高速缓存管理方案和基于优先级分配回写条目和传入核心请求的高速缓存管理方案来动态地选择。

公开(公告)号：US06173393B2

公开(公告)日：2001-01-09

申请号：US09052802

申请日：1998-03-31

申请人： Salvador Palanca ,  Vladimir M. Pentkovski ,  Suresh N. Kuttuva ,  Praveen B. Mosur

发明人： Salvador Palanca ,  Vladimir M. Pentkovski ,  Suresh N. Kuttuva ,  Praveen B. Mosur

IPC分类号： G06F1500

CPC分类号： G06F9/30032 ,  G06F9/30036

摘要： A processor comprising a decoder, an execution core and a bus controller. The decoder is operative to decode instructions received by the processor including a move instruction comprising a first operand identifying a plurality of bytes of packed data and a second operand identifying a corresponding plurality of byte masks. The execution core, coupled to the decoder, is operative to receive the decoded move instruction and analyze each individual byte mask of the plurality of byte masks to identify corresponding bytes within the plurality of bytes of packed data that are write-enabled. The bus controller, coupled to the execution core, is operative to write select bytes of the plurality of bytes of packed data to an implicitly defined location based, at least in part, on the write enabled byte masks identified by the execution core.

摘要翻译： 一种包括解码器，执行核心和总线控制器的处理器。 解码器用于解码由处理器接收的指令，包括移动指令，该移动指令包括标识多个字节的压缩数据的第一操作数和标识对应的多个字节掩码的第二操作数。 耦合到解码器的执行核心可操作以接收解码的移动指令并且分析多个字节掩码的每个单独的字节掩码以识别被写入使能的打包数据的多个字节内的相应字节。 耦合到执行核心的总线控制器可操作地至少部分地基于由执行核心识别的可写使能字节掩码，将多个打包数据的多个字节的选择字节写入隐式定义的位置。

公开(公告)号：US06434673B1

公开(公告)日：2002-08-13

申请号：US09607794

申请日：2000-06-30

申请人： Salvador Palanca ,  Lokpraveen B. Mosur

发明人： Salvador Palanca ,  Lokpraveen B. Mosur

IPC分类号： G06F1200

CPC分类号： G06F12/0859 ,  G06F12/0804

摘要： A method is provided that includes a step for setting a maximum number of concurrently allocated queue entries to service writeback evictions. The method also includes a step of setting a register bit based on cache requests. The method also includes a step for dynamically selecting, based on the register bit set, one of a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated in in any free entry based on priority. According to another embodiment of the invention, a computer system is provided that includes at least one computer processor. The computer processor provided has at least one cache memory and a cache controller. Further included is a register coupled to the computer processor. Also, a memory bus is provided that is coupled to the computer processor. A memory is included that is coupled to the memory bus. A controller for dynamically selecting between a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated based on priority is also included. The controller for dynamically selecting between one of a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated based on priority includes a register bit within the register that is capable of being set and cleared. The computer processor queries the register to determine if the register bit is either set and cleared.

摘要翻译： 提供了一种方法，其包括用于将并发分配的队列条目的最大数量设置为服务回写驱逐的步骤。 该方法还包括基于高速缓存请求设置寄存器位的步骤。 该方法还包括基于寄存器位集合动态地选择基于可编程回写条目的最大数量的高速缓存管理方案和允许将回写条目和进入的核心请求分配在其中的高速缓存管理方案的步骤 任何基于优先级的免费条目。 根据本发明的另一个实施例，提供一种包括至少一个计算机处理器的计算机系统。 提供的计算机处理器具有至少一个高速缓存存储器和高速缓存控制器。 还包括耦合到计算机处理器的寄存器。 而且，提供一个耦合到计算机处理器的存储器总线。 包括耦合到存储器总线的存储器。 还包括用于基于可编程回写条目的最大数量的高速缓存管理方案和允许基于优先级分配回写条目和传入核心请求的高速缓存管理方案之间的动态选择的控制器。 基于最大数量的可编程回写条目的高速缓存管理方案中的一个动态选择的控制器和允许基于优先级分配回写条目和传入核心请求的高速缓存管理方案包括：能够在该寄存器内的寄存器位 被设定和清除。 计算机处理器查询寄存器以确定寄存器位是置位还是清零。