公开(公告)号：US20200372851A1

公开(公告)日：2020-11-26

申请号：US16875682

申请日：2020-05-15

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Nam KIM ,  Sung Hoon LIM ,  Woo Geun LEE ,  Kyu Sik CHO ,  Jae Beom CHOI

IPC: G09G3/20

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

公开(公告)号：US20170110591A1

公开(公告)日：2017-04-20

申请号：US15246366

申请日：2016-08-24

Applicant: Samsung Display Co., Ltd.

Inventor： Seok Hwan BANG ,  Sook-Hwan BAN ,  Hyung Jun KIM ,  Woo Geun LEE ,  Hyeon Jun LEE

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/7869 ,  G02F1/136286 ,  G02F1/1368 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1262 ,  H01L27/3248 ,  H01L27/3276 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/458 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/78696

Abstract: One or more exemplary embodiments disclose a thin film transistor array panel and a manufacturing method thereof including a substrate, a gate line on the substrate, the gate line including a gate electrode, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, and the semiconductor layer including an oxide semiconductor, a data wire layer above the semiconductor layer, the data wire layer including a data line, a source electrode coupled to the data line, and a drain electrode facing the source electrode, and a metal phosphorus oxide layer configured to cover the source electrode and the drain electrode.