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    Semiconductor memory device
    22.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11521977B2

    公开(公告)日：2022-12-06

    申请号：US17471824

    申请日：2021-09-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok Lee ,  Chan-Sic Yoon ,  Augustin Hong ,  Keunnam Kim ,  Dongoh Kim ,  Bong-Soo Kim ,  Jemin Park ,  Hoin Lee ,  Sungho Jang ,  Kiwook Jung ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L27/24 ,  H01L27/22

    Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

    SEMICONDUCTOR DEVICES AND METHODS OF FORMING SEMICONDUCTOR DEVICES
    23.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FORMING SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210249418A1

    公开(公告)日：2021-08-12

    申请号：US17245203

    申请日：2021-04-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Taejin Park ,  Yoosang Hwang

    IPC: H01L27/108

    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.

    Semiconductor devices and methods of forming semiconductor devices
    24.
    发明授权
    Semiconductor devices and methods of forming semiconductor devices 有权

    公开(公告)号：US10998322B2

    公开(公告)日：2021-05-04

    申请号：US16295562

    申请日：2019-03-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Taejin Park ,  Yoosang Hwang

    IPC: H01L27/108

    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.

    SEMICONDUCTOR DEVICE
    25.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210111178A1

    公开(公告)日：2021-04-15

    申请号：US16909200

    申请日：2020-06-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jay-Bok Choi ,  Hyeonok Jung ,  Jemin Park ,  Yongseok Ahn

    IPC: H01L27/108 ,  H01L27/11548 ,  G11C7/06 ,  H01L27/11529

    Abstract: A semiconductor device includes a substrate having an active pattern, a cell region on the substrate and having a cell circuit, and a core region on the substrate having a peripheral circuit. In plan view, the active pattern on the core region includes a plurality of corners. Each of the corners has a rounding index that is equal to or less than about 15 nm. The rounding index is a distance between a respective tip of each of the corners and a right-angled corner.

    Methods of fabricating semiconductor memory devices
    26.
    发明授权
    Methods of fabricating semiconductor memory devices 有权

    公开(公告)号：US10559571B2

    公开(公告)日：2020-02-11

    申请号：US15952350

    申请日：2018-04-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunjung Kim ,  Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Semyeong Jang ,  Yoosang Hwang

    IPC: H01L21/02 ,  H01L27/108 ,  H01L21/768 ,  B08B7/00

    Abstract: A method of fabricating a semiconductor memory device includes forming a bit line and a bit line capping pattern on the semiconductor substrate, forming a first spacer covering a sidewall of the bit line capping pattern and a sidewall of the bit line, forming a contact plug in contact with a sidewall of the first spacer and having a top surface that is lower than an upper end of the first spacer, removing an upper portion of the first spacer, forming a first sacrificial layer closing at least an entrance of the void, forming a second spacer covering the sidewall of the bit line capping pattern and having a bottom surface in contact with a top surface of the first spacer, and removing the first sacrificial layer. The bit line capping pattern is on the bit line. The contact plug includes a void exposed on the top surface.

    Semiconductor devices with alignment keys
    28.
    发明授权
    Semiconductor devices with alignment keys 有权

    公开(公告)号：US10026694B2

    公开(公告)日：2018-07-17

    申请号：US15608747

    申请日：2017-05-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok Lee ,  Sooho Shin ,  Juik Lee ,  Jun Ho Lee ,  Kwangmin Kim ,  Ilyoung Moon ,  Jemin Park ,  Bumseok Seo ,  Chan-Sic Yoon ,  Hoin Lee

    IPC: H01L23/544 ,  H01L27/108

    Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.

    SEMICONDUCTOR DEVICES HAVING EXPANDED RECESS FOR BIT LINE CONTACT
    29.
    发明申请
    SEMICONDUCTOR DEVICES HAVING EXPANDED RECESS FOR BIT LINE CONTACT 有权
    具有扩展接口的半导体器件

    公开(公告)号：US20160181198A1

    公开(公告)日：2016-06-23

    申请号：US14971402

    申请日：2015-12-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： DAEIK KIM ,  Jemin Park ,  Sunghee Han ,  Yoosang Hwang

    IPC: H01L23/522 ,  H01L29/06 ,  H01L27/108

    CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10855 ,  H01L27/10897 ,  H01L29/4236 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a first device isolation region and a second device isolation region defining a first active region, a second active region, and a third active region in a substrate, a recess region exposing an upper surface of the first active region and upper surfaces of the first and second device isolation regions, and active buffer patterns on the second and third active regions. The first active region is located between the second and third active regions, the first device isolation region is located between the first and second active regions, the second device isolation region is located between the first and third active regions. Upper sidewalls of the second and third active regions are exposed in the recess region.

    Abstract translation: 半导体器件包括第一器件隔离区和限定衬底中的第一有源区，第二有源区和第三有源区的第二器件隔离区，暴露第一有源区的上表面的凹陷区和上表面 的第一和第二器件隔离区域以及第二和第三有效区域上的主动缓冲器图案。 第一有源区位于第二和第三有源区之间，第一器件隔离区位于第一和第二有源区之间，第二器件隔离区位于第一和第三有源区之间。 第二和第三有源区域的上侧壁在凹陷区域中露出。

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