公开(公告)号：US20240120263A1

公开(公告)日：2024-04-11

申请号：US18367896

申请日：2023-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHEOL KIM ,  HWANYOUNG CHOI ,  SEOKHYUN LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/373 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/3142 ,  H01L23/3672 ,  H01L23/373 ,  H01L23/49816 ,  H01L24/08 ,  H01L25/0655 ,  H01L2224/081 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438

Abstract: A semiconductor package includes a package substrate, an interposer mounted on the package substrate via first conductive bumps; first and second semiconductor devices on the interposer and spaced apart from each other, mounted on the interposer via second conductive bumps and having concavo-convex patterns respectively formed in upper surfaces thereof; and a sealing member on the interposer covering the first and second semiconductor devices and exposing the concavo-convex patterns. The concavo-convex pattern of the first semiconductor device includes a plurality of first pillar structures provided in the upper surface of a first region of the first semiconductor device and having a first width, and a plurality of second pillar structures provided in the upper surface of a second region of the first semiconductor device and having a second width greater than the first width.

公开(公告)号：US20230005842A1

公开(公告)日：2023-01-05

申请号：US17828799

申请日：2022-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINJUNG KIM ,  DONGKYU KIM ,  JONGYOUN KIM ,  SEOKHYUN LEE ,  JAEGWON JANG

IPC: H01L23/538 ,  H01L25/18

Abstract: A semiconductor package includes a substrate; and a first semiconductor device and a second semiconductor device that are provided on the substrate. The substrate includes a first dielectric layer and a second dielectric layer provided on the first dielectric layer, a plurality of signal lines provided between the first dielectric layer and the second dielectric layer and connecting the first semiconductor device to the second semiconductor device, and a conductive pad and a conductive plate provided on the second dielectric layer. The conductive pad overlaps the first semiconductor device or the second semiconductor device. The conductive plate overlaps the signal lines.

公开(公告)号：US20220328389A1

公开(公告)日：2022-10-13

申请号：US17535093

申请日：2021-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYEONJEONG HWANG ,  KYOUNG LIM SUK ,  SEOKHYUN LEE ,  JAEGWON JANG

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package comprises a first redistribution substrate including first interconnection layers sequentially stacked on each other, a semiconductor chip mounted on the first redistribution substrate, a mold layer disposed on the first redistribution substrate and surrounding the semiconductor chip, a second redistribution substrate disposed on the mold layer and including second interconnection layers sequentially stacked on each other, a connection terminal disposed beside the semiconductor chip to connect the first and second redistribution substrates to each other, and outer terminals disposed on a bottom surface of the first redistribution substrate. Each of the first and second interconnection layers may include an insulating layer and a wire pattern in the insulating layer. The first redistribution substrate may have substantially the same thickness as the second redistribution substrate, and the first interconnection layers may be thinner than the second interconnection layers.

公开(公告)号：US20220270959A1

公开(公告)日：2022-08-25

申请号：US17741751

申请日：2022-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEOKHYUN LEE ,  GWANGJAE JEON

IPC: H01L23/498

Abstract: Disclosed are redistribution substrates and semiconductor packages including the same. For example, a redistribution substrate including a dielectric pattern, and a first redistribution pattern in the dielectric pattern is provided. The first redistribution pattern may include: a first via part having a first via seed pattern and a first via conductive pattern on the first via seed pattern, and a first wiring part having a first wiring seed pattern and a first wiring conductive pattern, the first wiring part being disposed on the first via part and having a horizontal width that is different from a horizontal width of the first via part. Additionally, the first wiring seed pattern may cover a bottom surface and a sidewall surface of the first wiring conductive pattern, and the first via conductive pattern is directly connected to the first wiring conductive pattern.

公开(公告)号：US20220077007A1

公开(公告)日：2022-03-10

申请号：US17235997

申请日：2021-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： MINJUNG KIM ,  KYOUNG LIM SUK ,  SEOKHYUN LEE

IPC: H01L21/66 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate that includes a chip region and an edge region around the chip region, and a semiconductor chip on the chip region of the redistribution substrate. The redistribution substrate includes a plurality of dielectric layers that are vertically stacked, a plurality of redistribution patterns on the chip region and in each of the dielectric layers, and a redistribution test pattern on the edge region and at a level the same as a level of at least one of the redistribution patterns.

公开(公告)号：US20220037294A1

公开(公告)日：2022-02-03

申请号：US17184978

申请日：2021-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYEONJEONG HWANG ,  KYOUNG LIM SUK ,  SEOKHYUN LEE ,  JAEGWON JANG

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a first molding layer on the first redistribution substrate and covering a top surface and lateral surfaces of the first semiconductor chip, a second redistribution substrate on the first molding layer, and an adhesive film between the second redistribution substrate and the first molding layer. The adhesive film is spaced apart from the first semiconductor chip and covers a top surface of the first molding layer. A lateral surface of the adhesive film is coplanar with a lateral surface of the second redistribution substrate.

公开(公告)号：US20200098694A1

公开(公告)日：2020-03-26

申请号：US16696759

申请日：2019-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung Lim SUK ,  SEOKHYUN LEE

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/683 ,  H01L23/14 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: Insulating layers of a redistribution layer of a semiconductor package may be formed as a polymer film having inorganic fillers formed therein. The inorganic fillers may trap reactive materials to inhibit and/or substantially prevent the metal conductors, such as chip pads of the semiconductor chip being packaged, from being damaged by the reactive material. As a result, the reliability and the durability of the semiconductor package may be improved.

公开(公告)号：US20180366411A1

公开(公告)日：2018-12-20

申请号：US16006168

申请日：2018-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYOUNG LIM SUK ,  SEUNG-KWAN RYU ,  SEOKHYUN LEE

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

Abstract: A method of fabricating a semiconductor package includes forming a capping pattern on a chip pad of a semiconductor device. The semiconductor device includes a passivation pattern that exposes a portion of the chip pad, and the capping pattern covers the chip pad. The method further includes forming a redistribution layer on the capping pattern. Forming the redistribution layer includes forming a first insulation pattern on the capping pattern and the passivation pattern, forming a first opening in the first insulation pattern by performing exposure and development processes on the first insulation pattern, in which the first opening exposes a portion of the capping pattern, and forming a redistribution pattern in the first opening.