公开(公告)号：US20230005842A1

公开(公告)日：2023-01-05

申请号：US17828799

申请日：2022-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINJUNG KIM ,  DONGKYU KIM ,  JONGYOUN KIM ,  SEOKHYUN LEE ,  JAEGWON JANG

IPC: H01L23/538 ,  H01L25/18

Abstract: A semiconductor package includes a substrate; and a first semiconductor device and a second semiconductor device that are provided on the substrate. The substrate includes a first dielectric layer and a second dielectric layer provided on the first dielectric layer, a plurality of signal lines provided between the first dielectric layer and the second dielectric layer and connecting the first semiconductor device to the second semiconductor device, and a conductive pad and a conductive plate provided on the second dielectric layer. The conductive pad overlaps the first semiconductor device or the second semiconductor device. The conductive plate overlaps the signal lines.

公开(公告)号：US20220077007A1

公开(公告)日：2022-03-10

申请号：US17235997

申请日：2021-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： MINJUNG KIM ,  KYOUNG LIM SUK ,  SEOKHYUN LEE

IPC: H01L21/66 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate that includes a chip region and an edge region around the chip region, and a semiconductor chip on the chip region of the redistribution substrate. The redistribution substrate includes a plurality of dielectric layers that are vertically stacked, a plurality of redistribution patterns on the chip region and in each of the dielectric layers, and a redistribution test pattern on the edge region and at a level the same as a level of at least one of the redistribution patterns.

公开(公告)号：US20230326740A1

公开(公告)日：2023-10-12

申请号：US17994181

申请日：2022-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINJUNG KIM ,  HYUNGSUK MOON ,  SEUNGKOO SHIN ,  SANGHWANG PARK ,  HYEJOO YOON

IPC: H01L21/02 ,  H01L21/268

CPC classification number: H01L21/02126 ,  H01L21/02595 ,  H01L21/02532 ,  H01L21/268

Abstract: A substrate processing method includes; forming a silicon film on a substrate, irradiating the silicon film with microwaves, and soaking the silicon film in liquid heavy water.

公开(公告)号：US20220415771A1

公开(公告)日：2022-12-29

申请号：US17670635

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYEONJEONG HWANG ,  DONGKYU KIM ,  MINJUNG KIM ,  YEONHO JANG

IPC: H01L23/498 ,  H01L23/31

Abstract: A semiconductor package including a redistribution substrate extending in a first direction and a second direction perpendicular to the first direction, a semiconductor chip mounted on a top surface of the redistribution substrate, and an outer terminal on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern, a redistribution insulating layer covering a top surface and a side surface of the under-bump pattern, a protection pattern interposed between the top surface of the under-bump pattern and the redistribution insulating layer, and interposed between the side surface of the under-bump pattern and the redistribution insulating layer, and a redistribution pattern on the under-bump pattern. The outer terminal may be disposed on a bottom surface of the under-bump pattern.

公开(公告)号：US20230307334A1

公开(公告)日：2023-09-28

申请号：US17977167

申请日：2022-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： MINJUNG KIM ,  JONGBEOM PARK ,  JI-HYUN PARK

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49816 ,  H01L25/105 ,  H01L24/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/48 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2224/08235 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: A method of manufacturing a semiconductor package may include providing a semiconductor chip, forming redistribution patterns, which are provided on a top surface of the semiconductor chip and are electrically connected to the semiconductor chip, forming a protection layer to cover top surfaces of the redistribution patterns, forming under-bump protection patterns on the protection layer, and forming under-bump patterns, which are provided on the protection layer and are electrically connected to the redistribution patterns. The under-bump protection patterns may be spaced apart from each other.

公开(公告)号：US20230215799A1

公开(公告)日：2023-07-06

申请号：US18183062

申请日：2023-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYOUNG LIM SUK ,  KEUNG BEUM KIM ,  DONGKYU KIM ,  MINJUNG KIM ,  SEOKHYUN LEE

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L25/105 ,  H01L23/5386 ,  H01L23/5383 ,  H01L23/49822 ,  H01L21/4857 ,  H01L2924/14361 ,  H01L24/16 ,  H01L24/73 ,  H01L24/17 ,  H01L2924/1431 ,  H01L2224/08225 ,  H01L2924/1433 ,  H01L24/08 ,  H01L2225/1035 ,  H01L2224/16227 ,  H01L25/0652 ,  H01L25/18 ,  H01L24/33 ,  H01L2224/17181 ,  H01L2224/73253 ,  H01L2225/1058 ,  H01L2224/33181 ,  H01L2224/73204

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

公开(公告)号：US20230065378A1

公开(公告)日：2023-03-02

申请号：US17680857

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINJUNG KIM ,  DONGKYU KIM ,  JONGYOUN KIM ,  SEOKHYUN LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

Abstract: A semiconductor package includes a first redistribution substrate, a lower semiconductor chip on the first redistribution substrate and a through via therein, a first lower conductive structure and a second lower conductive structure that are on the first redistribution substrate and are laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and the second lower conductive structure and coupled to the through via and the second lower conductive structure, and an upper conductive structure on the first lower conductive structure. A width of the second lower conductive structure is greater than a width of the through via.

公开(公告)号：US20250167098A1

公开(公告)日：2025-05-22

申请号：US19029539

申请日：2025-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYOUNG LIM SUK ,  KEUNG BEUM KIM ,  DONGKYU KIM ,  MINJUNG KIM ,  SEOKHYUN LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

公开(公告)号：US20230065366A1

公开(公告)日：2023-03-02

申请号：US17806907

申请日：2022-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGKYU KIM ,  MINJUNG KIM ,  KYOUNG LIM SUK ,  SEOKHYUN LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes a first redistribution substrate, a passive device mounted on a bottom surface of the first redistribution substrate, a first semiconductor chip disposed on a top surface of the first redistribution substrate, the first semiconductor chip including a through via disposed therein, a second semiconductor chip disposed on the first semiconductor chip, and a conductive post disposed between the top surface of the first redistribution substrate and a bottom surface of the second semiconductor chip and spaced apart from the first semiconductor chip. The conductive post is connected to the first redistribution substrate and to the second semiconductor chip. The conductive post overlaps with at least a portion of the passive device in a vertical direction normal to the top surface of the first redistribution substrate.

公开(公告)号：US20230019311A1

公开(公告)日：2023-01-19

申请号：US17731416

申请日：2022-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINJUNG KIM ,  Dongkyu Kim ,  Jongyoun Kim ,  Hyeonjeong Hwang

IPC: H01L23/498 ,  H01L25/10

Abstract: A semiconductor package including: a first substrate and a semiconductor device on the first substrate, wherein the first substrate includes: a first dielectric layer including a first hole; a second dielectric layer on the first dielectric layer and including a second hole that overlaps the first hole, the second hole being wider than the first hole; an under bump disposed in the first hole and the second hole, the under bump covering a portion of the second dielectric layer; and a connection member bonded to the under bump.