公开(公告)号：US12224277B2

公开(公告)日：2025-02-11

申请号：US18149206

申请日：2023-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Bongsoon Lim ,  Hongsoo Jeon ,  Jaeduk Yu

IPC: H01L23/528 ,  G11C16/04 ,  G11C16/08 ,  H01L23/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/112

Abstract: A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.

公开(公告)号：US12217807B2

公开(公告)日：2025-02-04

申请号：US17960346

申请日：2022-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Yohan Lee

IPC: G11C7/22 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C11/56

Abstract: An operating method of a non-volatile memory device that includes a plurality of cell strings each including a first stack and a second stack adjacent to the first stack, the operating method include performing a first program operation during a time period in which a plurality of program loops are performed, by applying a program voltage including a first plurality of voltage levels to a select word line connected to the first stack of each of the plurality of cell strings, applying, during the time period, second voltages including a second plurality of voltage levels to a non-select word line connected to the first stack of each of the plurality of cell strings, and maintaining, during the time period, a third voltage at a first level, the third voltage applied to a non-select word line connected to the second stack of each of the plurality of cell strings.

公开(公告)号：US11854982B2

公开(公告)日：2023-12-26

申请号：US17982255

申请日：2022-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongsoon Lim ,  Sang-Wan Nam ,  Sang-Won Park ,  Sang-Won Shim ,  Hongsoo Jeon ,  Yonghyuk Choi

IPC: H01L23/535 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/535 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.

公开(公告)号：US11829645B2

公开(公告)日：2023-11-28

申请号：US17665926

申请日：2022-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk Yu ,  Bongsoon Lim ,  Yonghyuk Choi

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0679

Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.

公开(公告)号：US20230162807A1

公开(公告)日：2023-05-25

申请号：US17960346

申请日：2022-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Yohan Lee

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459

Abstract: An operating method of a non-volatile memory device that includes a plurality of cell strings each including a first stack and a second stack adjacent to the first stack, the operating method include performing a first program operation during a time period in which a plurality of program loops are performed, by applying a program voltage including a first plurality of voltage levels to a select word line connected to the first stack of each of the plurality of cell strings, applying, during the time period, second voltages including a second plurality of voltage levels to a non-select word line connected to the first stack of each of the plurality of cell strings, and maintaining, during the time period, a third voltage at a first level, the third voltage applied to a non-select word line connected to the second stack of each of the plurality of cell strings.

公开(公告)号：US11581297B2

公开(公告)日：2023-02-14

申请号：US17026637

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Bongsoon Lim ,  Hongsoo Jeon ,  Jaeduk Yu

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  G11C16/08 ,  G11C16/04

Abstract: A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.

公开(公告)号：US11275528B2

公开(公告)日：2022-03-15

申请号：US16891457

申请日：2020-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk Yu ,  Bongsoon Lim ,  Yonghyuk Choi

IPC: G06F3/06

Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.

公开(公告)号：US11158379B2

公开(公告)日：2021-10-26

申请号：US16935535

申请日：2020-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Jae-Duk Yu ,  Kang-Bin Lee ,  Sang-Won Shim ,  Bongsoon Lim

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C7/10 ,  G11C7/22 ,  G11C16/34 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11582 ,  H01L27/11556

Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

公开(公告)号：US11069417B2

公开(公告)日：2021-07-20

申请号：US16940935

申请日：2020-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk Yu ,  Bongsoon Lim ,  Yonghyuk Choi

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/32 ,  G11C16/26 ,  G11C16/30

Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.

公开(公告)号：US20210096967A1

公开(公告)日：2021-04-01

申请号：US16865948

申请日：2020-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

IPC: G06F11/20 ,  G11C16/04 ,  G11C16/08

Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.