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1.发明申请公开(公告)号：US20210065805A1
公开(公告)日：2021-03-04
申请号：US16851622
申请日：2020-04-17
发明人： Yonghyuk CHOI , Jae-Duk Yu , Kang-Bin Lee , Sang-Won Shim , Bongsoon Lim
摘要： Each of memory blocks of a nonvolatile memory device includes first memory cells of a first portion of pillar and second memory cells of a second portion of the pillar. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary.
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公开(公告)号：US10714184B2
公开(公告)日：2020-07-14
申请号：US16257768
申请日：2019-01-25
发明人： Sung-Min Joe , Kang-Bin Lee
IPC分类号： G11C16/04 , G11C16/10 , G11C11/4091 , G11C16/08 , G11C8/14 , G11C16/26 , G11C7/12 , G11C16/24
摘要： A method of operating a memory device includes performing a first program operation on memory cells connected to a first word line among a plurality of word lines, performing the first program operation on memory cells connected to a second word line among the plurality of word lines, applying a turn-on voltage at a first level to the first and second word lines, applying a voltage at a level lower than the first level to a third word line among the plurality of word lines, performing a precharge operation on partial cell strings among a plurality of cell strings, and performing a second program operation on the memory cells connected to the first word line.
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公开(公告)号：US09704590B2
公开(公告)日：2017-07-11
申请号：US15259765
申请日：2016-09-08
发明人： Sang-Wan Nam , Kang-Bin Lee , Junghoon Park
IPC分类号： G01C11/34 , G11C16/26 , G11C16/04 , G11C16/34 , H01L27/1157 , H01L27/11582 , G11C16/12 , G11C16/16
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/12 , G11C16/16 , G11C16/34 , G11C16/3459 , H01L27/1157 , H01L27/11582
摘要： An operating method of a nonvolatile memory, which includes a plurality of cell strings, each cell string having a plurality of memory cells and a string selection transistor stacked on a substrate, includes detecting threshold voltages of the string selection transistors of the plurality of cell strings; adjusting voltages to be supplied to the string selection transistors according to the detected threshold voltages; and applying the adjusted voltages to the string selection transistors to select or unselect the plurality of cell strings during a programming operation.
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公开(公告)号：US09466387B2
公开(公告)日：2016-10-11
申请号：US14790572
申请日：2015-07-02
发明人： Sang-Wan Nam , Kang-Bin Lee , Junghoon Park
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/12 , G11C16/16 , G11C16/34 , G11C16/3459 , H01L27/1157 , H01L27/11582
摘要： An operating method of a nonvolatile memory, which includes a plurality of cell strings, each cell string having a plurality of memory cells and a string selection transistor stacked on a substrate, includes detecting threshold voltages of the string selection transistors of the plurality of cell strings; adjusting voltages to be supplied to the string selection transistors according to the detected threshold voltages; and applying the adjusted voltages to the string selection transistors to select or unselect the plurality of cell strings during a programming operation.
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5.发明授权公开(公告)号：US11798629B2
公开(公告)日：2023-10-24
申请号：US17489988
申请日：2021-09-30
发明人： Yonghyuk Choi , Jae-Duk Yu , Kang-Bin Lee , Sang-Won Shim , Bongsoon Lim
IPC分类号： G11C7/14 , G11C16/10 , G11C16/08 , G11C16/34 , H01L25/065 , H01L25/18 , H01L23/00 , G11C16/04 , H10B41/27 , H10B43/27
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/08 , G11C16/349 , H01L24/05 , H01L24/08 , H01L25/0657 , H01L25/18 , H10B41/27 , H10B43/27 , H01L2224/05147 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
摘要： Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.
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公开(公告)号：US11600331B2
公开(公告)日：2023-03-07
申请号：US17524099
申请日：2021-11-11
发明人： Sung-Min Joe , Kang-Bin Lee
IPC分类号： G11C16/10 , G11C16/04 , G11C16/08 , G11C16/24 , H01L25/065 , H01L25/18 , H01L23/00 , H01L27/11556 , H01L27/11582
摘要： A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.
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公开(公告)号：US10892015B2
公开(公告)日：2021-01-12
申请号：US16822905
申请日：2020-03-18
发明人： Kang-Bin Lee , Il-Han Park , Jong-Hoo Jo
IPC分类号： G11C16/10 , G11C16/04 , G11C16/26 , G11C16/34 , G11C16/08 , H01L27/11556 , H01L27/11582
摘要： In a method of programming in a nonvolatile memory device, channels of a plurality of cell strings are precharged through ground selection transistors by a precharge voltage of a source line. A turn-on voltage is applied to a selected ground selection transistor of a selected cell string among the plurality of cell strings, during a verification read period of an N-th program loop. The turn-on voltage applied to the selected ground selection transistor is maintained to precharge the channels for an (N+1)-th program loop, without recovery after the verification read period of the N-th program loop is finished. Power consumption is reduced and an operation speed is increased by maintaining the turn-on voltage of the selected ground selection line to precharge the channels of the cell strings without recovery after the verification read operation is finished.
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公开(公告)号：US20200342942A1
公开(公告)日：2020-10-29
申请号：US16927100
申请日：2020-07-13
发明人： SUNG-MIN JOE , Kang-Bin Lee
IPC分类号： G11C16/10 , G11C16/04 , G11C16/08 , G11C16/24 , H01L25/065 , H01L25/18 , H01L23/00 , H01L27/11556 , H01L27/11582
摘要： A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.
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公开(公告)号：US20190267092A1
公开(公告)日：2019-08-29
申请号：US16257768
申请日：2019-01-25
发明人： SUNG-MIN JOE , Kang-Bin Lee
IPC分类号： G11C16/10 , G11C11/4091 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/04 , G11C7/12 , G11C8/14
摘要： A method of operating a memory device includes performing a first program operation on memory cells connected to a first word line among a plurality of word lines, performing the first program operation on memory cells connected to a second word line among the plurality of word lines, applying a turn-on voltage at a first level to the first and second word lines, applying a voltage at a level lower than the first level to a third word line among the plurality of word lines, performing a precharge operation on partial cell strings among a plurality of cell strings, and performing a second program operation on the memory cells connected to the first word line.
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10.发明授权公开(公告)号：US11158379B2
公开(公告)日：2021-10-26
申请号：US16935535
申请日：2020-07-22
发明人： Yonghyuk Choi , Jae-Duk Yu , Kang-Bin Lee , Sang-Won Shim , Bongsoon Lim
IPC分类号： G11C16/10 , G11C16/04 , G11C16/08 , G11C16/26 , G11C7/10 , G11C7/22 , G11C16/34 , H01L25/065 , H01L25/18 , H01L23/00 , H01L27/11582 , H01L27/11556
摘要： Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.
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