公开(公告)号：US20220352197A1

公开(公告)日：2022-11-03

申请号：US17244311

申请日：2021-04-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi MATSUNO ,  Johann ALSMEIER

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: Two types of support pillar structures are formed in a staircase region of an alternating stack of insulating layers and sacrificial material layers. First-type support pillar structures are formed in areas distal from backside trenches to be subsequently formed, and second-type support pillar structures may be formed in areas proximal to the backside trenches. The second-type support pillar structures may be formed as dielectric support pillar structures, or may be formed with at least one additional dielectric spacer.

公开(公告)号：US20220352091A1

公开(公告)日：2022-11-03

申请号：US17462446

申请日：2021-08-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin YU ,  Johann ALSMEIER ,  Koichi MATSUNO

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory opening fill structures including a respective vertical semiconductor channel and a respective memory film, and support pillar structures including a respective dummy vertical semiconductor channel, a respective dummy memory film, and a vertical stack of dielectric spacer fins located at levels of the electrically conductive layers and interposed between the electrically conductive layers and the respective dummy memory film.

公开(公告)号：US20220181348A1

公开(公告)日：2022-06-09

申请号：US17116093

申请日：2020-12-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi MATSUNO ,  Jixin YU ,  Johann ALSMEIER

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L23/522

Abstract: A three-dimensional memory device includes layer stacks located over a substrate and laterally spaced apart from each other by backside trenches. Each of the layer stacks includes a respective alternating stack of insulating layers and electrically conductive layers. Memory openings vertically extend through a respective one of the alternating stacks and are filled with a respective memory opening fill structure. Each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements. Each backside trench fill structure includes a respective row of backside trench bridge structures that are more distal from the substrate than a most distal one of the electrically conductive layers is from the substrate. The backside trench bridge structures can provide structural support during a replacement process that forms the electrically conductive layers.

公开(公告)号：US20240290714A1

公开(公告)日：2024-08-29

申请号：US18360461

申请日：2023-07-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mark D. KRAMAN ,  Johann ALSMEIER ,  James KAI ,  Koichi MATSUNO ,  Jixin YU ,  Ruogu Matthew ZHU ,  Seyyed Ehsan Esfahani RASHIDI

IPC: H01L23/528 ,  G11C16/04 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: H01L23/5283 ,  G11C16/0483 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings and including a respective memory film and a respective vertical semiconductor channel, contact wells vertically extending through a respective subset of layers of the alternating stack that includes a topmost insulating layer of the insulating layers, dielectric fill structures located in the contact wells, and an array of contact via structures vertically extending through the respective dielectric fill structure in each of the contact wells and contacting a top surface of a respective electrically conductive layer within a subset of the electrically conductive layers, the subset of the electrically conductive layers including a plurality of electrically conductive layers that are vertically spaced apart.

公开(公告)号：US20240251551A1

公开(公告)日：2024-07-25

申请号：US18358727

申请日：2023-07-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ruogu Matthew ZHU ,  Koichi MATSUNO ,  Seyyed Ehsan Esfahani RASHIDI ,  Jixin YU ,  Johann ALSMEIER

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes at least one alternating stack of respective insulating layers and respective electrically conductive layers and memory stack structures vertically extending through the at least one alternating stack. A layer contact via structure contacts a top surface of one of the electrically conductive layers, and is laterally surrounded by at least one dielectric spacer, which may include a plurality of dielectric spacers, and optionally by a plurality of dielectric support pillar structures. Additionally or alternatively, the layer contact via structure may comprise a convex surface segment that is adjoined to a straight sidewall segment.

公开(公告)号：US20240179905A1

公开(公告)日：2024-05-30

申请号：US18352726

申请日：2023-07-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takayuki MAEKURA ,  Takaaki IWAI ,  Hiroyuki OGAWA ,  Koichi MATSUNO

IPC: H10B43/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B43/10

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory cells. An integrated line-and-via structure is provided, which is a unitary structure including a metallic plate portion that is a portion of or laterally contacts an electrically conductive layer, and a metallic via portion that vertically extends through dielectric material plates that overlie the metallic plate portion.

公开(公告)号：US20240155841A1

公开(公告)日：2024-05-09

申请号：US18450791

申请日：2023-08-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seyyed Ehsan Esfahani RASHIDI ,  Yanli ZHANG ,  Koichi MATSUNO ,  James KAI

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A semiconductor structure includes alternating stacks of insulating layers and electrically conductive layers which are located over a substrate and are laterally spaced apart from each other by first backside trenches and second backside trenches that are interlaced along a horizontal direction, first backside trench fill structures located in the first backside trenches, and second backside trench fill structures located in the second backside trenches. Each of the first backside trench fill structures includes a respective set of first backside support bridge structures located at a first vertical spacing from the substrate, and each of the second backside trench fill structures includes a respective set of second backside support bridge structures located at a second vertical spacing from the substrate that is different from the first vertical spacing.

公开(公告)号：US20240057332A1

公开(公告)日：2024-02-15

申请号：US17819097

申请日：2022-08-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi MATSUNO

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565

Abstract: A three-dimensional memory device includes layer stacks each of which includes a first-tier alternating stack of first insulating layers and first electrically conductive layers and a second-tier alternating stack of second insulating layers and second electrically conductive layers separated by a backside trench. Memory opening fill structures vertically extend through a respective layer stack, and includes a respective vertical stack of memory elements and a respective vertical semiconductor channel. In one embodiment, a bridge structure spans an entire width of the backside trench such that a top surface of the bridge structure is located below a top surface of the second-tier alternating stack, and a bottom surface of the bridge structure is located above a bottom surface of the first-tier alternating stack. In another embodiment, a perforated bridge structure includes a plurality of vertically-extending openings.

公开(公告)号：US20240057331A1

公开(公告)日：2024-02-15

申请号：US17819081

申请日：2022-08-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi MATSUNO

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L23/522 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A three-dimensional memory device includes layer stacks each of which includes a first-tier alternating stack of first insulating layers and first electrically conductive layers and a second-tier alternating stack of second insulating layers and second electrically conductive layers separated by a backside trench. Memory opening fill structures vertically extend through a respective layer stack, and includes a respective vertical stack of memory elements and a respective vertical semiconductor channel. In one embodiment, a bridge structure spans an entire width of the backside trench such that a top surface of the bridge structure is located below a top surface of the second-tier alternating stack, and a bottom surface of the bridge structure is located above a bottom surface of the first-tier alternating stack. In another embodiment, a perforated bridge structure includes a plurality of vertically-extending openings.

公开(公告)号：US20220028846A1

公开(公告)日：2022-01-27

申请号：US16936047

申请日：2020-07-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Johann ALSMEIER ,  James KAI ,  Koichi MATSUNO

IPC: H01L25/18 ,  H01L25/00

Abstract: A bonded assembly includes a first three-dimensional memory die containing a first alternating stack of first insulating layers and first electrically conductive layers and first memory structures located in the first alternating stack, a second three-dimensional memory die bonded to the first three-dimensional memory die, and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory structures located in the second alternating stack. The first electrically conductive layers have different lateral extents along the first horizontal direction that decrease with a respective vertical distance from driver circuit devices, and the second electrically conductive layers have different lateral extents along the first horizontal direction that increase with the respective vertical distance from the driver circuit devices.