公开(公告)号：US20240250023A1

公开(公告)日：2024-07-25

申请号：US18358702

申请日：2023-07-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ruogu Matthew ZHU ,  Koichi MATSUNO ,  Seyyed Ehsan Esfahani RASHIDI ,  Jixin YU ,  Johann ALSMEIER

IPC: H01L23/528 ,  G11C5/06 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5283 ,  G11C5/063 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H01L23/5226

Abstract: A memory device includes at least one alternating stack of respective insulating layers and respective electrically conductive layers and memory stack structures vertically extending through the at least one alternating stack. A layer contact via structure contacts a top surface of one of the electrically conductive layers, and is laterally surrounded by at least one dielectric spacer, which may include a plurality of dielectric spacers, and optionally by a plurality of dielectric support pillar structures. Additionally or alternatively, the layer contact via structure may comprise a convex surface segment that is adjoined to a straight sidewall segment.

公开(公告)号：US20240290714A1

公开(公告)日：2024-08-29

申请号：US18360461

申请日：2023-07-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mark D. KRAMAN ,  Johann ALSMEIER ,  James KAI ,  Koichi MATSUNO ,  Jixin YU ,  Ruogu Matthew ZHU ,  Seyyed Ehsan Esfahani RASHIDI

IPC: H01L23/528 ,  G11C16/04 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: H01L23/5283 ,  G11C16/0483 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings and including a respective memory film and a respective vertical semiconductor channel, contact wells vertically extending through a respective subset of layers of the alternating stack that includes a topmost insulating layer of the insulating layers, dielectric fill structures located in the contact wells, and an array of contact via structures vertically extending through the respective dielectric fill structure in each of the contact wells and contacting a top surface of a respective electrically conductive layer within a subset of the electrically conductive layers, the subset of the electrically conductive layers including a plurality of electrically conductive layers that are vertically spaced apart.

公开(公告)号：US20240251551A1

公开(公告)日：2024-07-25

申请号：US18358727

申请日：2023-07-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ruogu Matthew ZHU ,  Koichi MATSUNO ,  Seyyed Ehsan Esfahani RASHIDI ,  Jixin YU ,  Johann ALSMEIER

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes at least one alternating stack of respective insulating layers and respective electrically conductive layers and memory stack structures vertically extending through the at least one alternating stack. A layer contact via structure contacts a top surface of one of the electrically conductive layers, and is laterally surrounded by at least one dielectric spacer, which may include a plurality of dielectric spacers, and optionally by a plurality of dielectric support pillar structures. Additionally or alternatively, the layer contact via structure may comprise a convex surface segment that is adjoined to a straight sidewall segment.

公开(公告)号：US20240155841A1

公开(公告)日：2024-05-09

申请号：US18450791

申请日：2023-08-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seyyed Ehsan Esfahani RASHIDI ,  Yanli ZHANG ,  Koichi MATSUNO ,  James KAI

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A semiconductor structure includes alternating stacks of insulating layers and electrically conductive layers which are located over a substrate and are laterally spaced apart from each other by first backside trenches and second backside trenches that are interlaced along a horizontal direction, first backside trench fill structures located in the first backside trenches, and second backside trench fill structures located in the second backside trenches. Each of the first backside trench fill structures includes a respective set of first backside support bridge structures located at a first vertical spacing from the substrate, and each of the second backside trench fill structures includes a respective set of second backside support bridge structures located at a second vertical spacing from the substrate that is different from the first vertical spacing.