公开(公告)号：US06570408B2

公开(公告)日：2003-05-27

申请号：US09931304

申请日：2001-08-16

申请人： Kevin John Nowka

发明人： Kevin John Nowka

IPC分类号： H03K19096

CPC分类号： H03K19/0019

摘要： In one aspect, a method for charge recovery in dynamic circuitry includes discharging a dynamic node during an evaluation interval by input circuitry coupled to the dynamic node responsive to one or more input signals. The discharging includes transferring the charge from the dynamic node to a capacitor during the evaluation time interval. The dynamic node is charged during a precharge interval by a voltage source and precharge timing circuitry coupled to the dynamic node responsive to a precharge signal. The charging includes transferring the charge from the capacitor back to the dynamic node.

摘要翻译： 一方面，一种用于动态电路中的电荷恢复的方法包括：响应于一个或多个输入信号，通过耦合到动态节点的输入电路在评估间隔期间对动态节点进行放电。 放电包括在评估时间间隔期间将电荷从动态节点转移到电容器。 动态节点在预充电间隔期间被电压源充电，并且响应于预充电信号耦合到动态节点的预充电定时电路。 充电包括将电荷从电容器转移回动态节点。

公开(公告)号：US06445217B1

公开(公告)日：2002-09-03

申请号：US09810026

申请日：2001-03-15

申请人： Nobuo Kojima ,  Kevin John Nowka ,  Huajun Wen

发明人： Nobuo Kojima ,  Kevin John Nowka ,  Huajun Wen

IPC分类号： H03F345

CPC分类号： H03K3/356156 ,  H03K3/037

摘要： An edge-triggered latch that incorporates pass-transistor logic (PTL) in the data and clock generation paths. In accordance with one embodiment, an edge-triggered latch includes a data input and at least one data path PTL transistor that passes data from the data input into a storage node in response to a latch trigger signal. A latch trigger circuit generates the latch-trigger signal in response to a clock signal transition.

摘要翻译： 在数据和时钟产生路径中集成了通过晶体管逻辑（PTL）的边沿触发锁存器。 根据一个实施例，边缘触发锁存器包括数据输入和至少一个数据通路PTL晶体管，其响应于锁存触发信号将数据从输入到存储节点的数据传送。 锁存触发电路响应时钟信号转换产生锁存触发信号。

公开(公告)号：US06441667B1

公开(公告)日：2002-08-27

申请号：US09820460

申请日：2001-03-29

申请人： David William Boerstler ,  Robert Keven Montoye ,  Kevin John Nowka

发明人： David William Boerstler ,  Robert Keven Montoye ,  Kevin John Nowka

IPC分类号： G06F104

CPC分类号： H03L7/087 ,  G06F1/04 ,  H03L7/091 ,  H03L7/0995 ,  Y10S331/02

摘要： The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate a control voltage which controls the frequency of the MVCO and to-generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.

摘要翻译： 同步状态输出与多相输出组合使用以产生和误差信号，该信号可用于产生控制电压，该控制电压控制MVCO的频率并产生移位的时钟，该时钟被分成顺序电路以产生 具有频率F的正交时钟

公开(公告)号：US06405231B1

公开(公告)日：2002-06-11

申请号：US09282270

申请日：1999-03-31

申请人： Kevin John Nowka

发明人： Kevin John Nowka

IPC分类号： G06F738

CPC分类号： G06F7/49957

摘要： An apparatus for rounding intermediate normalized mantissas within a floating-point processor is disclosed. The apparatus for rounding intermediate normalized mantissas within a floating-point processor includes an AND circuit, a selection circuit, and a multiplexor. The AND circuit generates an AND signal and its complement from a normalized mantissa. The selection circuit generates a select_AND signal and its complement from the normalized mantissa. The multiplexor, which is coupled to the AND circuit and the selection circuit, chooses either the AND signal or its complement signal as a rounded normalized mantissa according to the select_AND signal and its complement signal from the selection circuit.

摘要翻译： 公开了一种用于在浮点处理器内舍入中间标准化尾数的装置。 用于对浮点处理器内的中间归一化尾数进行舍入的装置包括与电路，选择电路和多路复用器。 “与”电路从标准化尾数生成一个“与”信号及其补码。 选择电路从标准化尾数生成一个select_AND信号及其补码。 耦合到AND电路和选择电路的多路复用器根据来自选择电路的select_AND信号及其补码信号，选择AND信号或其补码信号作为舍入的归一化尾数。

公开(公告)号：US08010066B2

公开(公告)日：2011-08-30

申请号：US12024448

申请日：2008-02-01

申请人： Juan-Antonio Carballo ,  Kevin John Nowka ,  Ivan Vo ,  Seung-moon Yoo

发明人： Juan-Antonio Carballo ,  Kevin John Nowka ,  Ivan Vo ,  Seung-moon Yoo

IPC分类号： H04B1/04

CPC分类号： H04L25/028 ,  H04L25/0272 ,  H04L25/0292

摘要： A digital transmission circuit and interface provide selectable power consumption via multiple weighted driver slices, improving the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.

摘要翻译： 数字传输电路和接口通过多个加权驱动器片提供可选择的功耗，提高接口的灵活性，同时在可能的同时降低发射机功耗，面积和复杂性。 级联的一系列驱动器级由一组并行片提供，并且控制逻辑激活一个或多个片，其组合以产生级联的有源驱动器电路。 切片组合的功耗/驱动器级别可选性提供了可以针对特定应用进行微调的驱动器，以在最小功耗级别提供所需的性能。

公开(公告)号：US20090302894A1

公开(公告)日：2009-12-10

申请号：US11859351

申请日：2007-09-21

申请人： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Kevin John Nowka

发明人： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Kevin John Nowka

IPC分类号： H03K19/20 ,  H03K19/096

CPC分类号： H03K19/0963

摘要： A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.

摘要翻译： 动态逻辑门具有用于在时钟的预充电阶段对动态节点充电的装置。 逻辑树在时钟的评估阶段使用设备来评估动态节点。 动态节点具有保持器电路，其包括反相器，其输入耦合到动态节点，其输出耦合到双栅极PFET器件的背栅极。 双栅极PFET的源极耦合到电源，并且其漏极耦合到形成半锁存器的动态节点。 双栅极PFET的前栅极耦合到具有模式输入和逻辑输入的逻辑电路，逻辑输入耦合回到感测动态节点的状态的节点。 模式输入可能是缓慢的模式，以保持动态节点状态或时钟延迟，在评估后打开强守护者。

公开(公告)号：US07522670B2

公开(公告)日：2009-04-21

申请号：US11050605

申请日：2005-02-03

申请人： Juan-Antonio Carballo ,  Kevin John Nowka ,  Ivan Vo ,  Seung-moon Yoo

发明人： Juan-Antonio Carballo ,  Kevin John Nowka ,  Ivan Vo ,  Seung-moon Yoo

IPC分类号： H04B3/00

CPC分类号： H04L25/028 ,  H04L25/0272 ,  H04L25/0292

摘要： A digital transmission circuit and method providing selectable power consumption via single-ended or differential operation improves the flexibility of an interface while reducing power consumption when possible. A differential path is provided through the transmitter output driver stages and portions are selectively disabled when the transmission circuit is in a lower-power operating mode. A single-ended to differential converter circuit can be used to construct a differential signal for output to the final driver stage. The selection of power mode can be made via feedback from a channel quality measurement unit or may be hardwired or selected under programmatic control. The longer delay or skew of the lower-power single-ended mode is compensated for by the relaxed requirements of the channel when conditions permit the use of the lower-power single-ended mode.

摘要翻译： 通过单端或差分操作提供可选择的功耗的数字传输电路和方法提高了接口的灵活性，同时在可能的同时降低功耗。 通过发射机输出驱动器级提供差分路径，并且当传输电路处于低功率操作模式时，部分被选择性地禁用。 单端到差分转换器电路可用于构建差分信号以输出到最终的驱动级。 可以通过来自信道质量测量单元的反馈来进行功率模式的选择，或者可以在编程控制下进行硬连线或选择。 当条件允许使用低功率单端模式时，较低功率单端模式的较长延迟或偏斜由信道的放宽要求进行补偿。

公开(公告)号：US07443195B2

公开(公告)日：2008-10-28

申请号：US10773427

申请日：2004-02-09

申请人： Juan-Antonio Carballo ,  Jeffrey L. Burns ,  Gary Dale Carpenter ,  Kevin John Nowka ,  Ivan Vo ,  Seung-moon Yoo

发明人： Juan-Antonio Carballo ,  Jeffrey L. Burns ,  Gary Dale Carpenter ,  Kevin John Nowka ,  Ivan Vo ,  Seung-moon Yoo

IPC分类号： H03K19/0175 ,  G05F1/10

CPC分类号： H03K19/0008

摘要： A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.

摘要翻译： 提供一种在保持性能特性的同时降低功耗并避免嵌入在SOC中的高速通信链路的昂贵的过度设计的方法。 该方法包括以降低的电压合成通信链路，以确定和隔离与非电源电压关键的电路相关的电源电压关键的电路。 电源电压关键电路包含不降低电压而不降低通信链路性能特性的组件。 使用非降低电压来驱动电源电压关键电路，同时使用降低的电压来驱动非电源电压关键电路。 使用嵌入在通信链路中的电压调节器来产生降低的电压。

公开(公告)号：US07265589B2

公开(公告)日：2007-09-04

申请号：US11168717

申请日：2005-06-28

申请人： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Kevin John Nowka

发明人： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Kevin John Nowka

IPC分类号： H03K19/20 ,  H03K19/094 ,  H03K19/00 ,  H03K19/096

CPC分类号： H03K19/0963

摘要： A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combination of the logic inputs. The logic tree has a stacked configuration with at least one multi-gate FEAT device for coupling an intermediate node of the logic tree to the dynamic node in response to a first logic input of the plurality of logic inputs or in response to the pre-charge phase of the clock signal. The multi-gate FEAT device has one gate coupled to the first logic input and a second gate coupled to a complement of the clock signal used to pre-charge the dynamic node.

摘要翻译： 动态逻辑门具有响应于时钟信号的预充电阶段和具有多个逻辑输入的逻辑树预充电的动态节点，用于在响应于时钟信号的时钟信号的估计阶段期间评估动态节点 逻辑输入的布尔组合。 逻辑树具有堆叠配置，其具有至少一个多栅极FEAT装置，用于响应于多个逻辑输入的第一逻辑输入或响应于预充电而将逻辑树的中间节点耦合到动态节点 时钟信号的相位。 多栅极FEAT器件具有耦合到第一逻辑输入的一个栅极和耦合到用于对动态节点预充电的时钟信号的补码的第二栅极。

公开(公告)号：US06836849B2

公开(公告)日：2004-12-28

申请号：US09826986

申请日：2001-04-05

申请人： Bishop Chapman Brock ,  Harm Peter Hofstee ,  Mark A. Johnson ,  Thomas Walter Keller, Jr. ,  Kevin John Nowka

发明人： Bishop Chapman Brock ,  Harm Peter Hofstee ,  Mark A. Johnson ,  Thomas Walter Keller, Jr. ,  Kevin John Nowka

IPC分类号： G06F126

CPC分类号： G06F1/3203

摘要： A method and controller for managing power and performance of a multiprocessor (MP) system is described. The controller receives sensor data corresponding to physical parameters within the MP system. The controller also receives quality of service and policy parameters corresponding to the MP system. The quality of service parameters define commitments to customers for utilization of the MP system. The policy parameters correspond to operation limits on inputs and outputs of the MP system. The operation input limits relate to the cost and availability of power or individual processor availability. The operation output limits relate to the amount of heat, acoustic noise levels, EMC levels, etc. that the individual or group of processors in the MP system are allowed to generate in a particular environment. A controller receives the physical parameters, the quality of service parameters and policy parameters and determines performance goals for the MP system and processors within the MP system. Then controller generates controls and applies them to individual processors to achieve the performance goals.

摘要翻译： 描述了一种用于管理多处理器（MP）系统的功率和性能的方法和控制器。 控制器接收与MP系统内的物理参数对应的传感器数据。 控制器还接收与MP系统对应的服务质量和策略参数。 服务质量参数定义了对客户使用MP系统的承诺。 策略参数对应于MP系统的输入和输出的操作限制。 操作输入限制涉及功率或单个处理器可用性的成本和可用性。 操作输出限制涉及允许MP系统中的个体或一组处理器在特定环境中生成的热量，声学噪声水平，EMC等级等。 控制器接收物理参数，服务质量参数和策略参数，并确定MP系统中的MP系统和处理器的性能目标。 然后控制器生成控件并将其应用于各个处理器以实现性能目标。