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27 条记录 (耗时 0.03 秒)

    Output driver
    22.
    发明授权
    Output driver 失效
    输出驱动

    公开(公告)号：US07999579B2

    公开(公告)日：2011-08-16

    申请号：US12165154

    申请日：2008-06-30

    申请人： Hyung-Dong Lee ,  Dong-Hwee Kim ,  Hwa-Yong Yang

    发明人： Hyung-Dong Lee ,  Dong-Hwee Kim ,  Hwa-Yong Yang

    IPC分类号： H03B1/00 ,  H03K3/00

    CPC分类号： H03K19/018521 ,  G11C7/1051 ,  G11C7/1054 ,  G11C11/4093

    摘要： An output driver is applicable to two or more interface standards. The output driver includes a pre-driver configured to generate pull-up control signals and pull-down control signals according to a logic value of data to be output and a target resistance, and adjust slew rates of the pull-up control signals and the pull-down control signals according to operation modes, and a driver configured to output the data in response to the pull-up and pull-down control signals.

    摘要翻译： 输出驱动器适用于两个或多个接口标准。 输出驱动器包括预驱动器，其被配置为根据要输出的数据的逻辑值和目标电阻产生上拉控制信号和下拉控制信号，并且调整上拉控制信号的转换速率和 根据操作模式的下拉控制信号，以及配置为响应于上拉和下拉控制信号输出数据的驱动器。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    23.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
    半导体集成电路

    公开(公告)号：US20100164605A1

    公开(公告)日：2010-07-01

    申请号：US12650592

    申请日：2009-12-31

    申请人： Jun-Ho LEE ,  Hyung-Dong Lee ,  Hyun-Seok Kim

    发明人： Jun-Ho LEE ,  Hyung-Dong Lee ,  Hyun-Seok Kim

    IPC分类号： G05F1/10

    CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit is capable of minimizing/decreasing the increase in the inductance of a package due to a power supply network thereof. The semiconductor integrated circuit includes a first power mesh configured to supply a first power to a first internal circuit, a second power mesh configured to supply a second power to a second internal circuit, the first power and the second power being used for different purposes and being equal in DC level, and a connection unit configured to connect the first power mesh to the second power mesh.

    摘要翻译： 半导体集成电路能够最小化/减少由于其电源网络而导致的封装的电感的增加。 半导体集成电路包括被配置为向第一内部电路提供第一功率的第一功率网格，被配置为将第二功率提供给第二内部电路的第二功率网，所述第一功率和所述第二功率用于不同的目的， 在DC电平上相等，以及连接单元，被配置为将第一电力网连接到第二电力网。

    Impedance-controlled pseudo-open drain output driver circuit and method for driving the same
    25.
    发明授权
    Impedance-controlled pseudo-open drain output driver circuit and method for driving the same 失效
    阻抗控制的开漏输出驱动电路及其驱动方法

    公开(公告)号：US07579861B2

    公开(公告)日：2009-08-25

    申请号：US11906365

    申请日：2007-10-01

    申请人： Dong-Suk Shin ,  Inhwa Jung ,  Chulwoo Kim ,  Hyung-Dong Lee ,  Young-Jung Choi

    发明人： Dong-Suk Shin ,  Inhwa Jung ,  Chulwoo Kim ,  Hyung-Dong Lee ,  Young-Jung Choi

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： H03K19/00384

    摘要： An impedance-controlled pseudo-open drain output driver circuit includes: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to output detection signals; a select signal generator configured to generate a driving select signal based on the detection signals and an output data; and an output driver configured to drive an output terminal, the output driver including a plurality of pull-up/pull-down driving blocks controlled by the driving select signal, each of the pull-up/pull-down driving blocks including a resistor having an intended impedance.

    摘要翻译： 阻抗控制的伪开漏输出驱动电路包括：处理电压和温度（PVT）检测器，被配置为具有接收参考时钟的延迟线，并根据PVT条件检测延迟线的状态变化以输出检测 信号; 选择信号发生器，被配置为基于所述检测信号和输出数据产生驱动选择信号; 以及输出驱动器，被配置为驱动输出端子，所述输出驱动器包括由所述驱动选择信号控制的多个上拉/下拉驱动块，每个所述上拉/下拉驱动块包括具有 一个预期的阻抗。

    Impedance-controlled pseudo-open drain output driver circuit and method for driving the same
    26.
    发明申请
    Impedance-controlled pseudo-open drain output driver circuit and method for driving the same 失效
    阻抗控制的开漏输出驱动电路及其驱动方法

    公开(公告)号：US20080079458A1

    公开(公告)日：2008-04-03

    申请号：US11906365

    申请日：2007-10-01

    申请人： Dong-Suk Shin ,  Inhwa Jung ,  Chulwoo Kim ,  Hyung-Dong Lee ,  Young-Jung Choi

    发明人： Dong-Suk Shin ,  Inhwa Jung ,  Chulwoo Kim ,  Hyung-Dong Lee ,  Young-Jung Choi

    IPC分类号： H03K19/0185

    CPC分类号： H03K19/00384

    摘要： An impedance-controlled pseudo-open drain output driver circuit includes: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to output detection signals; a select signal generator configured to generate a driving select signal based on the detection signals and an output data; and an output driver configured to drive an output terminal, the output driver including a plurality of pull-up/pull-down driving blocks controlled by the driving select signal, each of the pull-up/pull-down driving blocks including a resistor having an intended impedance.

    摘要翻译： 阻抗控制的伪开漏输出驱动电路包括：处理电压和温度（PVT）检测器，被配置为具有接收参考时钟的延迟线，并根据PVT条件检测延迟线的状态变化以输出检测 信号; 选择信号发生器，被配置为基于所述检测信号和输出数据产生驱动选择信号; 以及输出驱动器，被配置为驱动输出端子，所述输出驱动器包括由所述驱动选择信号控制的多个上拉/下拉驱动块，每个所述上拉/下拉驱动块包括具有 一个预期的阻抗。

    On-chip data transmission control apparatus and method
    27.
    发明申请
    On-chip data transmission control apparatus and method 失效

    公开(公告)号：US20060150044A1

    公开(公告)日：2006-07-06

    申请号：US11292734

    申请日：2005-12-01

    申请人： Hyung-Dong Lee ,  Eun-Jung Jang

    发明人： Hyung-Dong Lee ,  Eun-Jung Jang

    IPC分类号： G06F11/00 ,  G01R31/28

    CPC分类号： H04L25/4915

    摘要： The on-chip data transmission controller comprises a data comparison unit for comparing current data with previous data and issuing an inversion flag if the number of data bits phase-transited is larger than a preset number, a first data inversion unit for inverting a phase of the current data when the inversion flag is activated and providing inverted data onto a data bus, and a second data inversion unit for inverting a phase of the data transmitted via the data bus when the inversion flag is activated and outputting inverted data. Through this controller, an on-chip noise that largely occurs as the number of data to be transmitted increases can be reduced, by decreasing transition number of data inputted via the GIO line, in case of using a multi step pre-patch structure to improve an operation speed of a memory device.