公开(公告)号：US20080191212A1

公开(公告)日：2008-08-14

申请号：US12082495

申请日：2008-04-11

Applicant: Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

Inventor： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

IPC: H01L29/04

CPC classification number: H01L27/12 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1288

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

Abstract translation: 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在所述下导电膜的第一部分上形成像素电极; 去除下导电膜的第二部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US20060172472A1

公开(公告)日：2006-08-03

申请号：US11395434

申请日：2006-03-30

Applicant: Jeong-Young Lee ,  Se-Hwam Yu ,  Sang-Jin Jeon ,  Min-Wook Park

Inventor： Jeong-Young Lee ,  Se-Hwam Yu ,  Sang-Jin Jeon ,  Min-Wook Park

IPC: H01L29/04 ,  H01L21/84

CPC classification number: H01L27/12 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1288

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

Abstract translation: 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在所述下导电膜的第一部分上形成像素电极; 去除下导电膜的第二部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US20060103410A1

公开(公告)日：2006-05-18

申请号：US11217591

申请日：2005-08-31

Applicant: Sang-Jin Jeon

Inventor： Sang-Jin Jeon

IPC: G01R31/00

CPC classification number: G09G3/006

Abstract: A panel for a display device includes a display area and a peripheral area. The display area comprises a plurality of pixels each comprising a switching element and gate lines and data lines connected to the pixels. The peripheral area comprises a plurality of gate driving integrated circuit regions, a plurality of data driving integrated circuit regions, a plurality of repair lines disposed along the edge of the panel, connecting pads connected to both ends of the repair lines, a test line connected to at least one connecting pad, and a test pad connected to the test line. A test method for detecting disconnection of the data lines is also provided.

公开(公告)号：US20050082535A1

公开(公告)日：2005-04-21

申请号：US10926719

申请日：2004-08-26

Applicant: Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

Inventor： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

IPC: G02F1/136 ,  G02F1/133 ,  G02F1/1339 ,  G02F1/1368 ,  G03C1/85 ,  G03C5/00 ,  G09F9/30 ,  H01L21/00 ,  H01L21/336 ,  H01L29/786

CPC classification number: G02F1/1368 ,  G02F1/1339

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

Abstract translation: 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US20050030440A1

公开(公告)日：2005-02-10

申请号：US10884083

申请日：2004-07-01

Applicant: Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

Inventor： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

IPC: G02F1/13 ,  G02F1/1339 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/28 ,  H01L21/3205 ,  H01L23/52 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  G02F1/136

CPC classification number: H01L27/12 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1288

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

Abstract translation: 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在所述下导电膜的第一部分上形成像素电极; 去除下导电膜的第二部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US09164613B2

公开(公告)日：2015-10-20

申请号：US13299587

申请日：2011-11-18

Applicant: Sang-Jin Jeon ,  Ho-Kyoon Kwon

Inventor： Sang-Jin Jeon ,  Ho-Kyoon Kwon

IPC: G02F1/1335 ,  G02F1/1343 ,  G06F3/041 ,  G06F3/045 ,  G02F1/1333 ,  G02F1/1337 ,  G02F1/1362 ,  H01L29/417

CPC classification number: G06F3/0412 ,  G02F1/13338 ,  G02F1/133707 ,  G02F1/13624 ,  G02F2001/134318 ,  G02F2001/134345 ,  G02F2001/134381 ,  H01L29/41733

Abstract: A touch display substrate includes a first data line, a first gate line, a first pixel electrode, a second gate line, a second pixel electrode, a sensor data line and a first sensor electrode. The first data line extends along a first direction. The first gate line extends along a second direction. The first pixel electrode is electrically connected to the first data line and the first gate line. The second gate line is substantially parallel with the first gate line. The second pixel electrode is adjacent to the first pixel electrode and electrically connected to the first data line and the second gate line. The sensor data line is adjacent to the second pixel electrode and substantially parallel to the first data line. The first sensor electrode is electrically connected to the sensor data line.

Abstract translation: 触摸显示基板包括第一数据线，第一栅极线，第一像素电极，第二栅极线，第二像素电极，传感器数据线和第一传感器电极。 第一数据线沿着第一方向延伸。 第一栅极线沿第二方向延伸。 第一像素电极电连接到第一数据线和第一栅极线。 第二栅极线基本上与第一栅极线平行。 第二像素电极与第一像素电极相邻并且电连接到第一数据线和第二栅极线。 传感器数据线与第二像素电极相邻并且基本上平行于第一数据线。 第一传感器电极电连接到传感器数据线。

公开(公告)号：US09109055B2

公开(公告)日：2015-08-18

申请号：US14112849

申请日：2012-08-24

Applicant: Won-Hee Kim ,  Kyung-Seop Noh ,  Nan-Young Lee ,  Sang-Jin Jeon

Inventor： Won-Hee Kim ,  Kyung-Seop Noh ,  Nan-Young Lee ,  Sang-Jin Jeon

IPC: C08F4/64 ,  C08F4/76 ,  B01J23/00 ,  B01J21/06 ,  C08F10/00

CPC classification number: C08F4/76 ,  B01J21/06 ,  C08F4/64 ,  C08F4/659 ,  C08F10/00 ,  C08F4/64141 ,  C08F4/65908 ,  C08F210/16 ,  C08F210/14 ,  C08F2500/03

Abstract: The present invention relates to a transition metal catalyst composition which can exhibit high reactivity in a polymerization reaction of a polyolefin and can easily control characteristics such as chemical structure, molecular weight distribution, mechanical properties, and the like of a synthesized polyolefin, and a method of preparing a polyolefin using the catalyst composition.

Abstract translation: 本发明涉及能够在聚烯烃的聚合反应中表现出高反应性的过渡金属催化剂组合物，并且可以容易地控制合成聚烯烃的化学结构，分子量分布，机械性能等特性，以及方法 使用该催化剂组合物制备聚烯烃。

公开(公告)号：US09035006B2

公开(公告)日：2015-05-19

申请号：US13980869

申请日：2012-01-19

Applicant: Sang-Jin Jeon ,  Seung-Ki Park ,  Kyung-Seop Noh ,  Nan-Young Lee ,  Won-Hee Kim ,  Sang-Eun An

Inventor： Sang-Jin Jeon ,  Seung-Ki Park ,  Kyung-Seop Noh ,  Nan-Young Lee ,  Won-Hee Kim ,  Sang-Eun An

IPC: C08F210/16 ,  C08F295/00 ,  C08J5/18 ,  C08F297/08 ,  C08F301/00

CPC classification number: C08F295/00 ,  C08F210/16 ,  C08F297/08 ,  C08F301/00 ,  C08F2500/10 ,  C08J5/18 ,  C08J2323/16

Abstract: The present description relates to an olefin block copolymer preferably useful to form nonslip pads due to excellences in elasticity and heat resistance, and a sheet-shaped molded body comprising the olefin block copolymer The olefin block copolymer includes a plurality of blocks or segments, each of which includes an ethylene or propylene repeating unit and an α-olefin repeating unit at different weight fractions. The olefin block copolymer satisfies a defined relationship when a load of 5 to 10 kg is applied to a sheet-shaped molded body of the block copolymer for 12 hours or longer at a temperature of 60° C. or higher, and then removed.

Abstract translation: 本发明涉及由于弹性和耐热性优异而优选用于形成非滑垫的烯烃嵌段共聚物和包含烯烃嵌段共聚物的片状成型体。烯烃嵌段共聚物包括多个嵌段或链段 其包括乙烯或丙烯重复单元和不同重量分数的α-烯烃重复单元。 当在60℃以上的温度下对嵌段共聚物的片状成型体施加5〜10kg的负荷12小时以上时，烯烃嵌段共聚物满足规定的关系，然后除去。

公开(公告)号：US08759461B2

公开(公告)日：2014-06-24

申请号：US13386282

申请日：2010-07-23

Applicant: Sang-Jin Jeon ,  Hoon Chae ,  Cheon-Il Park ,  Kyung-Seop Noh ,  Won-Hee Kim

Inventor： Sang-Jin Jeon ,  Hoon Chae ,  Cheon-Il Park ,  Kyung-Seop Noh ,  Won-Hee Kim

IPC: C08F4/76 ,  C08F4/64 ,  C08F4/52

CPC classification number: C07D215/12

Abstract: The present invention relates to a novel post metallocene-type ligand compound, to a metal compound containing the ligand compound, to a catalytic composition containing the metal compound, and to a method for preparing same, as well as to a method for preparing olefin polymers using the catalytic composition. The present invention provides a catalyst for preparing special polyolefin-based polymers having excellent activity.

Abstract translation: 本发明涉及一种新颖的后茂金属型配体化合物，含有配体化合物的金属化合物，涉及含有金属化合物的催化组合物及其制备方法，以及制备烯烃聚合物的方法 使用催化剂组合物。 本发明提供一种制备具有优异活性的特种聚烯烃基聚合物的催化剂。

公开(公告)号：US08003988B2

公开(公告)日：2011-08-23

申请号：US12612448

申请日：2009-11-04

Applicant: Sang-Jin Jeon

Inventor： Sang-Jin Jeon

IPC: H01L29/04 ,  H01L29/10 ,  G02F1/1333 ,  H01L21/00

CPC classification number: G02F1/136204 ,  G02F1/136259 ,  G02F2001/133388 ,  G02F2001/134318 ,  G02F2001/136263 ,  G02F2001/136272 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2330/04 ,  G09G2330/08 ,  H01L27/124

Abstract: A thin film transistor array panel comprises a repair line disposed in a peripheral area of a display area and being configured to repair when at least one of a gate line and a data line are disconnected, and a detour line disposed in the peripheral area and comprising at least one resistor having higher resistance than a remaining portion of the detour line, wherein both ends of the detour line are connected to the repair line to protect the array panel.

Abstract translation: 薄膜晶体管阵列面板包括设置在显示区域的外围区域中的修复线，并且被配置为当栅极线和数据线中的至少一个断开时进行修复，以及设置在周边区域中的迂回线，并且包括 至少一个电阻器具有比绕行线路的剩余部分更高的电阻，其中绕线的两端连接到修复线以保护阵列面板。