公开(公告)号：US06559500B2

公开(公告)日：2003-05-06

申请号：US09927387

申请日：2001-08-13

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: H01L29788

CPC classification number: H01L27/11568 ,  G11C16/0466 ,  G11C16/0491 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/115 ,  H01L29/792

Abstract: First and second impurity diffusion regions are disposed in partial surface layers of a semiconductor substrate and spaced apart by some distance. A gate electrode is formed above a channel region defined between the first and second impurity diffusion regions. A gate insulating film is disposed between the channel region and gate electrode. Of the gate insulating film, a portion thereof disposed at least in a partial area along the longitudinal direction of a path interconnecting the first and second impurity diffusion regions, having a lamination structure of a first insulating film, a charge trap film and a second insulating film sequentially stacked in this order. The charge trap film is made of insulating material easier to trap electrons than the first and second insulating films. A control circuit drains holes trapped in each film between the gate electrode and the channel region or at an interface between adjacent films, by applying a hole drain voltage to the gate electrode, the hole drain voltage being higher than a voltage applied to either the first or second impurity diffusion region.

公开(公告)号：US08089808B2

公开(公告)日：2012-01-03

申请号：US12413052

申请日：2009-03-27

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: G11C16/94 ,  G11C16/86

CPC classification number: H01L27/11529 ,  G11C16/0433 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11546

Abstract: A nonvolatile semiconductor memory including a memory cell array of memory cells arranged in a matrix, each of which includes a selective transistor and a memory cell transistor; the first column decoder for controlling the potentials of the bit lines and the source lines; the first row decoder for controlling the potential of the first word lines; the second row decoder for controlling the potential of the second word lines; and the second column decoder. The first column decoder includes a circuit whose withstand voltage is lower than the first row decoder and the second column decoder, and the second row decoder includes a circuit whose withstand voltage is lower than the first row decoder and the second column decoder.

Abstract translation: 一种非易失性半导体存储器，包括以矩阵形式布置的存储单元的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 用于控制位线和源极线的电位的第一列解码器; 用于控制第一字线的电位的第一行解码器; 用于控制第二字线的电位的第二行解码器; 和第二列解码器。 第一列解码器包括其耐受电压低于第一行解码器和第二列解码器的电路，并且第二行解码器包括其耐受电压低于第一行解码器和第二列解码器的电路。

公开(公告)号：US08014204B2

公开(公告)日：2011-09-06

申请号：US12892388

申请日：2010-09-28

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: G11C11/34

CPC classification number: H01L27/11568 ,  G11C16/0433 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11565 ,  H01L29/7881

Abstract: A semiconductor device includes a first memory cell which includes a first memory transistor and a first selector transistor. The semiconductor device further includes a second memory cell which includes a second memory transistor and a second selector transistor. The semiconductor device further includes a first word line electrically coupled to a gate electrode of the first memory transistor and to a gate electrode of the second selector transistor, and a second word line electrically coupled to a gate electrode of the second memory transistor and to a gate electrode of the first selector transistor. The semiconductor device further includes a first source line electrically coupled to a source region of the first memory transistor and to a source region of the second memory transistor.

Abstract translation: 半导体器件包括第一存储单元，其包括第一存储晶体管和第一选择晶体管。 半导体器件还包括第二存储单元，其包括第二存储晶体管和第二选择晶体管。 半导体器件还包括电耦合到第一存储晶体管的栅电极和第二选择晶体管的栅电极的第一字线，以及电耦合到第二存储晶体管的栅电极的第二字线， 第一选择晶体管的栅电极。 半导体器件还包括电耦合到第一存储晶体管的源极区域和第二存储晶体管的源极区域的第一源极线。

公开(公告)号：US07764546B2

公开(公告)日：2010-07-27

申请号：US12405947

申请日：2009-03-17

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: G11C16/00

CPC classification number: G11C16/3418

Abstract: Embodiments of the present invention disclose a method of utilizing a flash memory array to decrease programming time while maintaining sufficient read speeds. An array of cells is programmed and read in pages that are oriented in the column direction, parallel to the bit lines in the array. An erased cell in the present invention is a cell in the “off” state. According to the present invention a cell is programmed by lowering the threshold voltage of the cell, thereby turning the cell “on.” An array of cells is programmed read in a sector-by-sector method, wherein a sector consists of units situated diagonally adjacent to each other, and a unit consists of multiple parallel column-oriented pages.

Abstract translation: 本发明的实施例公开了一种利用闪存阵列来减少编程时间同时保持足够的读取速度的方法。 单元格阵列被编程和读取在与列方向相对齐的页面上，与阵列中的位线平行。 本发明中的擦除单元是处于“关闭”状态的单元。 根据本发明，通过降低单元的阈值电压来对单元进行编程，从而使单元“导通”。以逐扇式方法对单元阵列进行编程，其中扇区由对角线 彼此相邻，并且单元由多个平行的面向列的页面组成。

公开(公告)号：US07675104B2

公开(公告)日：2010-03-09

申请号：US11461131

申请日：2006-07-31

Applicant: Amol Ramesh Joshi ,  Harpreet Sachar ,  YouSeok Suh ,  Shenqing Fang ,  Chih-Yuh Yang ,  Lovejeet Singh ,  David H. Matsumoto ,  Hidehiko Shiraiwa ,  Kuo-Tung Chang ,  Scott A. Bell ,  Allison Holbrook ,  Satoshi Torii

Inventor： Amol Ramesh Joshi ,  Harpreet Sachar ,  YouSeok Suh ,  Shenqing Fang ,  Chih-Yuh Yang ,  Lovejeet Singh ,  David H. Matsumoto ,  Hidehiko Shiraiwa ,  Kuo-Tung Chang ,  Scott A. Bell ,  Allison Holbrook ,  Satoshi Torii

IPC: H01L21/8247

CPC classification number: H01L27/11568 ,  H01L21/3081 ,  H01L21/76224 ,  H01L27/115 ,  H01L29/66833

Abstract: An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.

Abstract translation: 一种集成电路存储器系统，包括：提供衬底; 在所述衬底上形成富硅电荷存储层; 通过富硅电荷存储层沿第一方向形成第一隔离沟槽; 以及在第二方向上通过富硅电荷存储层形成第二隔离沟槽。

公开(公告)号：US20100032745A1

公开(公告)日：2010-02-11

申请号：US12537913

申请日：2009-08-07

Applicant: Tatsuya Sugimachi ,  Satoshi Torii

Inventor： Tatsuya Sugimachi ,  Satoshi Torii

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  H01L21/823468 ,  H01L27/11524 ,  H01L29/6656

Abstract: A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer.

Abstract translation: 半导体器件包括：存储单元晶体管，其具有浮置栅极，控制栅极，以及经由沟道区域形成在浮置栅极两侧的半导体衬底中的源极和漏极; 以及选择晶体管，其具有在所述选择栅极的两侧上形成在所述半导体衬底中的选择栅极和源极和漏极，其中所述选择晶体管的源极连接到所述存储单元晶体管的漏极， 存储单元晶体管具有N型第一杂质扩散层，比第一杂质扩散层更深的N型第二杂质扩散层和比第二杂质扩散层浅的N型第三杂质扩散层， 第二杂质扩散层的杂质浓度低于第三杂质扩散层的杂质浓度。

公开(公告)号：US20090180321A1

公开(公告)日：2009-07-16

申请号：US12413052

申请日：2009-03-27

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: G11C16/04 ,  G11C16/06

CPC classification number: H01L27/11529 ,  G11C16/0433 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11546

Abstract: A nonvolatile semiconductor memory including a memory cell array of memory cells arranged in a matrix, each of which includes a selective transistor and a memory cell transistor; the first column decoder for controlling the potentials of the bit lines and the source lines; the first row decoder for controlling the potential of the first word lines; the second row decoder for controlling the potential of the second word lines; and the second column decoder. The first column decoder includes a circuit whose withstand voltage is lower than the first row decoder and the second column decoder, and the second row decoder includes a circuit whose withstand voltage is lower than the first row decoder and the second column decoder.

Abstract translation: 一种非易失性半导体存储器，包括以矩阵形式布置的存储单元的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 用于控制位线和源极线的电位的第一列解码器; 用于控制第一字线的电位的第一行解码器; 用于控制第二字线的电位的第二行解码器; 和第二列解码器。 第一列解码器包括其耐受电压低于第一行解码器和第二列解码器的电路，并且第二行解码器包括其耐受电压低于第一行解码器和第二列解码器的电路。

公开(公告)号：US07423312B1

公开(公告)日：2008-09-09

申请号：US10896292

申请日：2004-07-20

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: H01L29/788

CPC classification number: H01L29/7883 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513

Abstract: The present invention provides an apparatus and method for a non-volatile memory comprising at least one array of memory cells with shallow trench isolation (STI) regions between bit lines for increased process margins. Specifically, in one embodiment, each of the memory cells in the array of memory cells includes a source, a control gate, and a drain, and is capable of storing at least one bit. The array of memory cells further includes word lines that are coupled to control gates of memory cells. The word lines are arranged in rows in the array. In addition, the array comprises bit lines coupled to source and drains of memory cells. The bit lines are arranged in columns in the array. Also, the array comprises at least one row of bit line contacts for providing electrical conductivity to the bit lines. Further, the array comprises shallow trench isolation (STI) regions separating each of the bit lines along the row of bit line contacts.

Abstract translation: 本发明提供了一种用于非易失性存储器的装置和方法，该装置和方法包括在位线之间的浅沟槽隔离（STI）区域的至少一个存储单元阵列，用于增加工艺裕度。 具体地，在一个实施例中，存储单元阵列中的每个存储单元包括源极，控制栅极和漏极，并且能够存储至少一个位。 存储单元阵列还包括耦合到存储器单元的控制栅极的字线。 字线在数组中排成行。 此外，阵列包括耦合到存储器单元的源极和漏极的位线。 位线排列在数组中的列中。 而且，该阵列包括用于向位线提供导电性的至少一行位线触点。 此外，阵列包括沿着位线触点行分隔每个位线的浅沟槽隔离（STI）区域。

公开(公告)号：US07092297B1

公开(公告)日：2006-08-15

申请号：US10899684

申请日：2004-07-26

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: G11C16/04

CPC classification number: G11C16/3468 ,  G11C16/3477

Abstract: The present invention provides a method for erasing floating gate memory devices. Specifically, one embodiment of the present invention discloses a method for erasing an array of non-volatile flash memory cells arranged in a plurality of rows and a plurality of columns. A plurality of word lines are coupled to the plurality of rows. The embodiment of the method begins by applying a positive voltage to odd word lines in the plurality of word lines in a first phase of an erase cycle. The plurality of word lines comprising alternating odd and even word lines. The embodiment continues by applying a negative voltage to even word lines in the plurality of word lines in the first phase of the erase cycle. Then, the embodiment applies the negative voltage to the odd word lines in the plurality of word lines in a second phase of said erase cycle. Thereafter, the embodiment continues by applying the positive voltage to the even word lines in the second phase of the erase cycle.

Abstract translation: 本发明提供一种擦除浮动栅极存储器件的方法。 具体地，本发明的一个实施例公开了一种擦除以多行和多列布置的非易失性闪存单元阵列的方法。 多个字线耦合到多个行。 该方法的实施例开始于在擦除周期的第一阶段中对多个字线中的奇数字线施加正电压。 多个字线包括交替的奇数和偶数字线。 该实施例通过在擦除周期的第一阶段中对多个字线中的偶数字线施加负电压来继续。 然后，本实施例在所述擦除周期的第二阶段中将负电压施加到多个字线中的奇数字线。 此后，本实施例通过在擦除周期的第二阶段中对偶数字线施加正电压来继续。

公开(公告)号：US06947326B2

公开(公告)日：2005-09-20

申请号：US10618712

申请日：2003-07-15

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: G11C16/02 ,  G11C16/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/34 ,  G11C29/56

CPC classification number: G11C16/3445 ,  G11C16/3436 ,  G11C16/3459

Abstract: A first decision process, which reads data from a memory cell under a first deciding condition to decide pass/fail and applies a signal to the memory cell to change an amount of charge stored in the memory cell if the data is decided as fail, and a second decision process, which reads the data from the memory cell under a second deciding condition that is relaxed rather than the first deciding condition to decide the pass/fail, are executed, and then the processes are repeated from the first decision process when the data is decided as fail in the second decision process.