公开(公告)号：US20110292751A1

公开(公告)日：2011-12-01

申请号：US13205820

申请日：2011-08-09

申请人： Tyler Thorp ,  Roy E. Scheuerlein

发明人： Tyler Thorp ,  Roy E. Scheuerlein

IPC分类号： G11C7/04

CPC分类号： G11C7/04 ,  G11C16/06

摘要： Apparatus and systems are provided for thermal regulation of a memory integrated circuit (“IC”). The apparatus and systems may include a thermal sensor on a memory IC, and a heating element coupled to the thermal sensor. The heating element is adapted to heat the memory IC in response to a signal from the thermal sensor. Other aspects are also provided.

摘要翻译： 提供了用于存储器集成电路（“IC”）的热调节的装置和系统。 该装置和系统可以包括存储器IC上的热传感器和耦合到热传感器的加热元件。 加热元件适于响应于来自热传感器的信号来加热存储器IC。 还提供其他方面。

公开(公告)号：US20110266514A1

公开(公告)日：2011-11-03

申请号：US13182960

申请日：2011-07-14

申请人： S. Brad Herner ,  Roy E. Scheuerlein

发明人： S. Brad Herner ,  Roy E. Scheuerlein

IPC分类号： H01L45/00 ,  B82Y99/00

CPC分类号： H01L27/101 ,  B82Y10/00 ,  G11C13/025 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/149

摘要： A memory cell is provided, the memory cell including a steering element having a vertically-oriented p-i-n junction, and a carbon nanotube fabric. The steering element and the carbon nanotube fabric are arranged electrically in series, and the entire memory cell is formed above a substrate. Other aspects are also provided.

摘要翻译： 提供了一种存储单元，所述存储单元包括具有垂直取向的p-i-n结的转向元件和碳纳米管织物。 导向元件和碳纳米管织物电串联布置，整个存储单元形成在基板上。 还提供其他方面。

公开(公告)号：US08040721B2

公开(公告)日：2011-10-18

申请号：US12551546

申请日：2009-08-31

申请人： Tyler Thorp ,  Roy E. Scheuerlein

发明人： Tyler Thorp ,  Roy E. Scheuerlein

IPC分类号： G11C11/00

CPC分类号： G11C13/0011 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/77

摘要： The present invention provides methods and apparatus for adjusting voltages of bit and word lines to create short programming pulses to program a memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a second line connected to the memory cell to a predetermined voltage from a second line standby voltage, switching the first line from the first voltage to a second voltage, and switching the first line from the second voltage to the first voltage. The voltage difference between the first voltage and the predetermined voltage is such that a safe voltage results that does not program the memory cell. A voltage difference between the second voltage and the predetermined voltage is such that a programming voltage operative to program the memory cell results. The switching operations together may create a first pulse.

摘要翻译： 本发明提供了用于调整位和字线的电压以产生编程脉冲以编程存储器单元的方法和装置。 本发明可以包括将连接到存储器单元的第一线路从第一线路备用电压设置为第一电压，将连接到存储器单元的第二线路从第二线路待机电压充电到预定电压，将第一线路从 第一电压到第二电压，并且将第一线路从第二电压切换到第一电压。 第一电压和预定电压之间的电压差使得不对存储单元进行编程的安全电压。 第二电压和预定电压之间的电压差使得可操作以编程存储器单元的编程电压结果。 一起切换操作可以产生第一脉冲。

公开(公告)号：US20110210305A1

公开(公告)日：2011-09-01

申请号：US13083746

申请日：2011-04-11

申请人： S. Brad Herner ,  Roy E. Scheuerlein

发明人： S. Brad Herner ,  Roy E. Scheuerlein

IPC分类号： H01L45/00 ,  H01L21/8239 ,  B82Y30/00

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L27/2481 ,  H01L27/285 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/149 ,  H01L51/0048 ,  H01L51/0595 ,  Y10S977/742

摘要： A method of programming a carbon nanotube memory cell is provided, wherein the memory cell comprises a first conductor, a steering element, a carbon nanotube fabric, and a second conductor, wherein the steering element and the carbon nanotube fabric are arranged electrically in series between the first conductor and the second conductor, and wherein the entire carbon nanotube memory cell is formed above a substrate, the carbon nanotube fabric having a first resistivity, the method including applying a first electrical set pulse between the first conductor and the second conductor, wherein, after application of the first electrical set pulse, the carbon nanotube fabric has a second resistivity, the second resistivity less than the first resistivity. Other aspects are also provided.

摘要翻译： 提供了一种编程碳纳米管存储单元的方法，其中存储单元包括第一导体，操舵元件，碳纳米管织物和第二导体，其中所述操舵元件和所述碳纳米管织物串联地电排列在 第一导体和第二导体，并且其中整个碳纳米管存储单元形成在衬底上方，所述碳纳米管织物具有第一电阻率，所述方法包括在所述第一导体和所述第二导体之间施加第一电脉冲，其中 在施加第一电气设备脉冲之后，碳纳米管织物具有第二电阻率，第二电阻率小于第一电阻率。 还提供其他方面。

公开(公告)号：US08004919B2

公开(公告)日：2011-08-23

申请号：US12828846

申请日：2010-07-01

申请人： Tyler J. Thorp ,  Roy E. Scheuerlein

发明人： Tyler J. Thorp ,  Roy E. Scheuerlein

IPC分类号： G11C7/04

CPC分类号： G11C7/04 ,  G11C16/06

摘要： Apparatus and systems are provided for thermal regulation of a memory integrated circuit (“IC”). The apparatus and systems may include a thermal sensor on a memory IC, and a heating element coupled to the thermal sensor. The heating element is adapted to heat the memory IC in response to a signal from the thermal sensor. Other aspects are also provided.

摘要翻译： 提供了用于存储器集成电路（“IC”）的热调节的装置和系统。 该装置和系统可以包括存储器IC上的热传感器和耦合到热传感器的加热元件。 加热元件适于响应于来自热传感器的信号来加热存储器IC。 还提供其他方面。

公开(公告)号：US07982209B2

公开(公告)日：2011-07-19

申请号：US11692148

申请日：2007-03-27

申请人： S. Brad Herner ,  Roy E. Scheuerlein

发明人： S. Brad Herner ,  Roy E. Scheuerlein

IPC分类号： H01L29/06

CPC分类号： H01L27/101 ,  B82Y10/00 ,  G11C13/025 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/149

摘要： A rewritable nonvolatile memory cell is disclosed comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of the carbon nanotube fabric can be sensed, and can correspond to distinct data states of the memory cell. A first memory level of such memory cells can be monolithically formed above a substrate, a second memory level monolithically formed above the first, and so on, forming a highly dense monolithic three dimensional memory array of stacked memory levels.

摘要翻译： 公开了一种可重写的非易失性存储单元，其包括与碳纳米管织物串联的转向元件。 转向元件优选为二极管，但也可以是晶体管。 当经受适当的电脉冲时，碳纳米管织物可逆地改变电阻率。 可以感测碳纳米管织物的不同电阻率状态，并且可以对应于存储器单元的不同数据状态。 这种存储器单元的第一存储器级别可以单片地形成在衬底上方，第一存储器级单元形成在第一存储器之上，等等，形成堆叠存储器级别的高密度单片三维存储器阵列。

公开(公告)号：US20110149631A1

公开(公告)日：2011-06-23

申请号：US12643561

申请日：2009-12-21

申请人： Roy E. Scheuerlein ,  Luca Fasoli

发明人： Roy E. Scheuerlein ,  Luca Fasoli

IPC分类号： G11C17/00 ,  G11C7/00

CPC分类号： G11C11/5692 ,  G11C16/349 ,  G11C17/16 ,  G11C2211/5641 ,  G11C2211/5646

摘要： The embodiments described herein are directed to a memory device with multi-level, write-once memory cells. In one embodiment, a memory device has a memory array comprising a plurality of multi-level write-once memory cells, wherein each memory cell is programmable to one of a plurality of resistivity levels. The memory device also contains circuitry configured to select a group of memory cells from the memory array, and read a set of flag bits associated with the group of memory cells. The set of flag bits indicate a number of times the group of memory cells has been written to. The circuitry is also configured to select a threshold read level appropriate for the number of times the group of memory cells has been written to, and for each memory cell in the group, read the memory cell as an unprogrammed single-bit memory cell or as a programmed single-bit memory cell based on the selected threshold read level.

摘要翻译： 这里描述的实施例涉及具有多级，一次写入存储器单元的存储器件。 在一个实施例中，存储器装置具有包括多个多级一次写入存储器单元的存储器阵列，其中每个存储器单元可编程为多个电阻率水平中的一个。 存储器件还包含被配置为从存储器阵列中选择一组存储器单元的电路，并且读取与该组存储器单元相关联的一组标志位。 该组标志位指示存储器单元组被写入的次数。 电路还被配置为选择适合于已经写入存储器单元组的次数的阈值读取电平，并且对于组中的每个存储器单元，读取作为未编程的单位存储器单元的存储器单元或者作为 基于所选择的阈值读取电平的编程的单位存储器单元。

公开(公告)号：US07961494B2

公开(公告)日：2011-06-14

申请号：US12242417

申请日：2008-09-30

申请人： Roy E. Scheuerlein

发明人： Roy E. Scheuerlein

IPC分类号： G11C11/00

CPC分类号： G11C11/5685 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C17/16 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/19 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/72 ,  Y10T29/49002

摘要： A very dense cross-point memory array of multi-level read/write two-terminal memory cells, and methods for its programming, are described. Multiple states are achieved using two or more films that each have bi-stable resistivity states, rather than “tuning” the resistance of a single resistive element. An exemplary memory cell includes a vertical pillar diode in series with two different bi-stable resistance films. Each bi-stable resistance film has both a high resistance and low resistance state that can be switched with appropriate application of a suitable bias voltage and current. Such a cross-point array is adaptable for two-dimensional rewritable memory arrays, and also particularly well-suited for three-dimensional rewritable (3D R/W) memory arrays.

摘要翻译： 描述了多级读/写两端存储单元的非常密集的交叉点存储器阵列及其编程方法。 使用两个或更多个具有双稳态电阻率状态的膜而不是“调谐”单个电阻元件的电阻来实现多个状态。 示例性存储单元包括与两个不同的双稳电阻膜串联的立柱二极管。 每个双稳态电阻膜具有高电阻和低电阻状态，可以适当地施加适当的偏置电压和电流来切换。 这种交叉点阵列适用于二维可重写存储器阵列，并且还特别适用于三维可重写（3D R / W）存储器阵列。

公开(公告)号：US07924602B2

公开(公告)日：2011-04-12

申请号：US12693782

申请日：2010-01-26

申请人： S. Brad Herner ,  Roy E. Scheuerlein

发明人： S. Brad Herner ,  Roy E. Scheuerlein

IPC分类号： G11C11/00

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L27/2481 ,  H01L27/285 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/149 ,  H01L51/0048 ,  H01L51/0595 ,  Y10S977/742

摘要： A method of programming a carbon nanotube memory cell is provided, wherein the memory cell comprises a first conductor, a steering element, a carbon nanotube fabric, and a second conductor, wherein the steering element and the carbon nanotube fabric are arranged electrically in series between the first conductor and the second conductor, and wherein the entire carbon nanotube memory cell is formed above a substrate, the carbon nanotube fabric having a first resistivity, the method including applying a first electrical set pulse between the first conductor and the second conductor, wherein, after application of the first electrical set pulse, the carbon nanotube fabric has a second resistivity, the second resistivity less than the first resistivity. Other aspects are also provided.

摘要翻译： 提供了一种编程碳纳米管存储单元的方法，其中存储单元包括第一导体，操舵元件，碳纳米管织物和第二导体，其中所述操舵元件和所述碳纳米管织物串联地电排列在 第一导体和第二导体，并且其中整个碳纳米管存储单元形成在衬底上方，所述碳纳米管织物具有第一电阻率，所述方法包括在所述第一导体和所述第二导体之间施加第一电脉冲，其中 在施加第一电气设备脉冲之后，碳纳米管织物具有第二电阻率，第二电阻率小于第一电阻率。 还提供其他方面。

公开(公告)号：US20110051505A1

公开(公告)日：2011-03-03

申请号：US12551548

申请日：2009-08-31

申请人： Tyler Thorp ,  Roy E. Scheuerlein

发明人： Tyler Thorp ,  Roy E. Scheuerlein

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0061 ,  G11C13/0069

摘要： The present invention provides methods and apparatus for adjusting voltages of bit and word lines to program a two terminal memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a second line connected to the memory cell to a predetermined voltage from a second line standby voltage, and switching the first line from the first voltage to a second voltage. The voltage difference between the first voltage and the predetermined voltage is such that a safe voltage results that does not program the memory cell. A voltage difference between the second voltage and the predetermined voltage is such that a programming voltage operative to program the memory cell results.

摘要翻译： 本发明提供了调节位和字线的电压以编程两个终端存储单元的方法和装置。 本发明可以包括将连接到存储器单元的第一线路从第一线路待机电压设置为第一电压，将连接到存储器单元的第二线路从第二线路待机电压充电到预定电压，以及将第一线路从 第一电压到第二电压。 第一电压和预定电压之间的电压差使得不对存储单元进行编程的安全电压。 第二电压和预定电压之间的电压差使得可操作以编程存储器单元的编程电压结果。