公开(公告)号：US08385120B2

公开(公告)日：2013-02-26

申请号：US12910063

申请日：2010-10-22

申请人： Joon-Suc Jang ,  Ki-Hwan Choi ,  Duck-Kyun Woo ,  Si-Hwan Kim

发明人： Joon-Suc Jang ,  Ki-Hwan Choi ,  Duck-Kyun Woo ,  Si-Hwan Kim

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/3418

摘要： A method of programming a nonvolatile memory device is provided. The method includes providing a plurality of memory cells coupled to a wordline, the plurality of memory cells grouped into a plurality of groups, each group including at least two memory cells, such that for each cell of the plurality of memory cells that has memory cells adjacent both sides, the memory cells immediately adjacent either side of the cell belong to different groups from each other. The method further includes selecting one group from the plurality of groups, and performing a program operation including applying a program pulse to the selected group while one or more non-selected groups of the plurality of groups are inhibited from being programmed.

摘要翻译： 提供了一种编程非易失性存储器件的方法。 所述方法包括提供耦合到字线的多个存储器单元，所述多个存储器单元分组成多个组，每个组包括至少两个存储器单元，使得对于具有存储器单元的多个存储器单元中的每个单元 相邻两侧，紧邻细胞两侧的存储单元彼此不同。 该方法还包括从多个组中选择一个组，并且执行编程操作，包括在禁止编程多个组中的一个或多个未选择的组时将编程脉冲施加到所选择的组。

公开(公告)号：US07778084B2

公开(公告)日：2010-08-17

申请号：US12071011

申请日：2008-02-14

申请人： Moo-Sung Kim ,  Ki-Hwan Choi

发明人： Moo-Sung Kim ,  Ki-Hwan Choi

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/3436 ,  G11C2211/5621

摘要： Non-volatile memory devices and operating methods thereof are provided. In an operating method, a first operation is performed by applying a first voltage to at least one word line. The first operation includes one of a programming or erasing operation. The first operation is verified by applying a verify voltage to each of the at least one word lines. The voltage level of each verify voltage is determined according to position information of a corresponding one of the at least one word lines.

摘要翻译： 提供非易失性存储器件及其操作方法。 在操作方法中，通过对至少一个字线施加第一电压来执行第一操作。 第一操作包括编程或擦除操作之一。 通过对至少一个字线中的每一个应用验证电压来验证第一操作。 每个验证电压的电压电平根据至少一个字线中对应的一个字线的位置信息来确定。

公开(公告)号：US07489558B2

公开(公告)日：2009-02-10

申请号：US11700834

申请日：2007-02-01

申请人： Ki-Hwan Choi ,  Young-Ho Lim

发明人： Ki-Hwan Choi ,  Young-Ho Lim

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： The present invention provides a program method of a flash memory device including a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The memory cells are subjected to a primary program operation. Those memory cells arranged within a specific region of respective states are subjected to a secondary program operation to have a threshold voltage equivalent to or higher than a verify voltage used in the primary program operation. Thus, although a threshold voltage distribution is widened due to an electric field coupling/F-poly coupling and HTS, a read margin between adjacent states may be sufficiently secured using the program method.

摘要翻译： 本发明提供了一种闪速存储装置的编程方法，其包括用于存储指示多个状态之一的多位数据的多个存储单元。 对存储器单元进行主程序操作。 布置在各个状态的特定区域内的那些存储单元经受二次编程操作，以具有等于或高于在主程序操作中使用的验证电压的阈值电压。 因此，尽管由于电场耦合/ F-poly耦合和HTS而使阈值电压分布变宽，但是可以使用编程方法充分确保相邻状态之间的读取余量。

公开(公告)号：US20080205160A1

公开(公告)日：2008-08-28

申请号：US12071011

申请日：2008-02-14

申请人： Moo-Sung Kim ,  Ki-Hwan Choi

发明人： Moo-Sung Kim ,  Ki-Hwan Choi

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/3436 ,  G11C2211/5621

摘要： Non-volatile memory devices and operating methods thereof are provided. In an operating method, a first operation is performed by applying a first voltage to at least one word line. The first operation includes one of a programming or erasing operation. The first operation is verified by applying a verify voltage to each of the at least one word lines. The voltage level of each verify voltage is determined according to position information of a corresponding one of the at least one word lines.

摘要翻译： 提供非易失性存储器件及其操作方法。 在操作方法中，通过对至少一个字线施加第一电压来执行第一操作。 第一操作包括编程或擦除操作之一。 通过对至少一个字线中的每一个应用验证电压来验证第一操作。 每个验证电压的电压电平根据至少一个字线中对应的一个字线的位置信息来确定。

公开(公告)号：US06914827B2

公开(公告)日：2005-07-05

申请号：US10430364

申请日：2003-05-05

申请人： Ki-Hwan Choi

发明人： Ki-Hwan Choi

IPC分类号： G11C11/34 ,  G11C16/34 ,  G11C7/00

CPC分类号： G11C16/3418 ,  G11C16/3468 ,  G11C16/3477

摘要： The flash memory device according to the present invention includes an erase control circuit, used as a state machine, having embodied erase algorithm which can prevent flash memory cells from being over-erased. The erase control circuit, first, checks whether or not threshold voltages of selected cells reach a predetermined pre-verify voltage higher than the maximum value of a target threshold voltage range corresponding to the erased state. When at least one of the selected cells has its threshold voltage higher than the pre-verify voltage, a high voltage generator generates a bulk voltage that is increased step by step by a predetermined voltage level. And, when the selected cells all have threshold voltages equal to or less than the pre-verify voltage, the high voltage generator generates a constant bulk voltage. According to this bulk voltage control scheme, the number of flash memory cells over-erased at the erase operation is reduced reducing the total erase time.

摘要翻译： 根据本发明的闪速存储器件包括用作状态机的具有实现的擦除算法的擦除控制电路，其可以防止闪速存储器单元被过度擦除。 擦除控制电路首先检查所选择的单元的阈值电压是否达到比对应于擦除状态的目标阈值电压范围的最大值高的预定预验证电压。 当所选择的单元中的至少一个具有高于预验证电压的阈值电压时，高电压发生器产生逐步增加预定电压电平的体电压。 并且，当所选择的单元都具有等于或小于预验证电压的阈值电压时，高电压发生器产生恒定的体电压。 根据该体电压控制方案，在擦除操作时被擦除的闪存单元的数量减少，减少了总擦除时间。

公开(公告)号：US06577540B2

公开(公告)日：2003-06-10

申请号：US10016579

申请日：2001-11-01

申请人： Ki-Hwan Choi

发明人： Ki-Hwan Choi

IPC分类号： G11C700

CPC分类号： G11C16/3468

摘要： The flash memory device according to the present invention includes an erase control circuit, used as a state machine, having embodied erase algorithm which can prevent flash memory cells from being over-erased. The erase control circuit, first, checks whether or not threshold voltages of selected cells reach a predetermined pre-verify voltage higher than the maximum value of a target threshold voltage range corresponding to the erased state. When at least one of the selected cells has its threshold voltage higher than the pre-verify voltage, a high voltage generator generates a bulk voltage that is increased step by step by a predetermined voltage level. And, when the selected cells all have threshold voltages equal to or less than the pre-verify voltage, the high voltage generator generates a constant bulk voltage. According to this bulk voltage control scheme, the number of flash memory cells over-erased at the erase operation is reduced reducing the total erase time.

公开(公告)号：US06483747B2

公开(公告)日：2002-11-19

申请号：US10138002

申请日：2002-05-03

申请人： Ki-Hwan Choi ,  Jong-Min Park

发明人： Ki-Hwan Choi ,  Jong-Min Park

IPC分类号： G11C1604

CPC分类号： G11C16/107 ,  G11C16/3404

摘要： A method is disclosed for preventing over-erasure in a nonvolatile memory device having a plurality of sectors, each sector including a main field and a redundant field. The method includes the steps of programming memory cells included in the main and redundant fields, erasing the memory cells included in the main and redundant fields, and programming over-erased cells of the memory cells included in the main and redundant fields. The main and redundant fields are included in a sector.

公开(公告)号：US06249461B1

公开(公告)日：2001-06-19

申请号：US09593260

申请日：2000-06-13

申请人： Ki-Hwan Choi ,  Jong-Min Park

发明人： Ki-Hwan Choi ,  Jong-Min Park

IPC分类号： G11C1600

CPC分类号： G11C16/26 ,  G11C2216/20 ,  H04L27/30

摘要： Is herein disclosed a flash memory device which provides a status read operation for indicating its status of operation. In the flash memory device, a first group of data output circuits are coupled to first data input/output pins each of which outputs a status data signal associated with the status read operation. A second group of data output circuits are coupled to second data input/output pins each of which is reserved during the status read operation. A data output circuit coupled to at least one of the first data input/output pins generates a toggled status data signal so that the toggled status data signal to be outputted via the at least one pin at an Nth cycle of an output enable signal is generated at a (N-1)th cycle of the output enable signal during the status read operation. Each of the second data input/output pins is maintained at a predetermined state(e.g., ‘1’, ‘0’ or Hi-Z) by a corresponding data input/output circuit during the status read operation.

摘要翻译： 这里公开了一种闪存设备，其提供用于指示其操作状态的状态读取操作。 在闪速存储器件中，第一组数据输出电路耦合到第一数据输入/输出引脚，每个引脚输出与状态读取操作相关联的状态数据信号。 第二组数据输出电路耦合到第二数据输入/输出引脚，每个引脚在状态读取操作期间被保留。 耦合到第一数据输入/输出引脚中的至少一个的数据输出电路产生切换的状态数据信号，以便产生在输出使能信号的第N个周期经由至少一个引脚输出的触发状态数据信号 在状态读取操作期间的输出使能信号的第（N-1）个周期。 在状态读取操作期间，通过相应的数据输入/输出电路将每个第二数据输入/输出引脚保持在预定状态（例如，“1”，“0”或“Hi-Z”）。

公开(公告)号：US06181606B2

公开(公告)日：2001-01-30

申请号：US09428816

申请日：1999-10-28

申请人： Ki-Hwan Choi ,  Jong-Min Park

发明人： Ki-Hwan Choi ,  Jong-Min Park

IPC分类号： G11C1606

CPC分类号： G11C16/12 ,  G11C16/08

摘要： Nonvolatile integrated circuit memory devices include a memory cell array having a plurality of rows of memory cells therein that are electrically coupled to respective word lines. A word line driver circuit is provided having a plurality of outputs electrically coupled to the word lines. A preferred voltage supply control circuit is also provided. This voltage supply control circuit is responsive to a verify enable signal and a flag signal and powers the word line driver circuit at a first voltage level when the verify enable signal is inactive or the flag signal is active, and powers the word line driver circuit at a second voltage level greater than the first voltage level when the verify enable signal is active and the flag signal is inactive. The first voltage level corresponds to a power supply voltage level Vcc and the second voltage level corresponds to a boosted voltage level Vpp having a magnitude that exceeds a magnitude of the power supply voltage level Vcc. The memory device also comprises a program/erase verification control circuit that generates an active verify enable signal continuously during a verification time interval and generates an active flag signal as a series of pulses during the verification time interval. Because the generation of an active flag signal results in the generation of a word line voltage having reduced magnitude, smaller pull-down transistors can be used within the word line driver circuit and higher integration densities can therefore be achieved.

摘要翻译： 非易失性集成电路存储器件包括其中具有多个存储单元的行的存储单元阵列，其电耦合到相应的字线。 提供了具有电耦合到字线的多个输出的字线驱动器电路。 还提供了优选的电压供应控制电路。 该电压供应控制电路响应于验证使能信号和标志信号，并且当验证使能信号无效或标志信号有效时，以第一电压电平为字线驱动器电路供电，并且在字线驱动器电路 当验证使能信号有效且标志信号无效时，第二电压电平大于第一电压电平。 第一电压电平对应于电源电压电平Vcc，第二电压电平对应于具有超过电源电压电平Vcc的幅度的幅度的升压电压电平Vpp。 存储装置还包括一个编程/擦除验证控制电路，其在验证时间间隔期间连续地产生一个有效的验证使能信号，并且在验证时间间隔期间产生一个有效标志信号作为一系列的脉冲。 因为产生有效标志信号导致产生具有降低的幅度的字线电压，所以可以在字线驱动电路内使用更小的下拉晶体管，因此可以实现更高的集成密度。