公开(公告)号：US20070183210A1

公开(公告)日：2007-08-09

申请号：US11700834

申请日：2007-02-01

申请人： Ki-Hwan Choi ,  Young-Ho Lim

发明人： Ki-Hwan Choi ,  Young-Ho Lim

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： The present invention provides a program method of a flash memory device including a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The memory cells are subjected to a primary program operation. Those memory cells arranged within a specific region of respective states are subjected to a secondary program operation to have a threshold voltage equivalent to or higher than a verify voltage used in the primary program operation. Thus, although a threshold voltage distribution is widened due to an electric field coupling/F-poly coupling and HTS, a read margin between adjacent states may be sufficiently secured using the program method.

摘要翻译： 本发明提供了一种闪速存储装置的编程方法，其包括用于存储指示多个状态之一的多位数据的多个存储单元。 对存储器单元进行主程序操作。 布置在各个状态的特定区域内的那些存储单元经受二次编程操作，以具有等于或高于在主程序操作中使用的验证电压的阈值电压。 因此，尽管由于电场耦合/ F-poly耦合和HTS而使阈值电压分布变宽，但是可以使用编程方法充分确保相邻状态之间的读取余量。

公开(公告)号：US06222772B1

公开(公告)日：2001-04-24

申请号：US09506997

申请日：2000-02-18

申请人： Ki-Hwan Choi ,  Jong-Min Park

发明人： Ki-Hwan Choi ,  Jong-Min Park

IPC分类号： G11C1600

CPC分类号： G11C16/3445 ,  G11C16/16

摘要： An electrically erasable and programmable non-volatile semiconductor memory device and method of erasing the same device are provided. A fail bit counter is provided for the device and method. The fail bit counter counts erase fail bits during the sector erase operation. An erase control circuit selectively terminates the sector erase operation depending upon erase fail bit number.

摘要翻译： 提供了一种电可擦除和可编程的非易失性半导体存储器件以及擦除相同器件的方法。 为设备和方法提供故障位计数器。 故障位计数器在扇区擦除操作期间计数擦除失败位。 擦除控制电路根据擦除失败位数选择性地终止扇区擦除操作。

公开(公告)号：US6137729A

公开(公告)日：2000-10-24

申请号：US213723

申请日：1998-12-17

申请人： Ki-Hwan Choi

发明人： Ki-Hwan Choi

IPC分类号： G11C16/02 ,  G11C16/06 ,  G11C16/16 ,  G11C16/00

CPC分类号： G11C16/16 ,  G11C2216/20

摘要： A method for erasing electrically erasable and programmable memory cells arranged in a plurality of sectors, in a memory device receiving a suspend command and a resume command, the erasing having steps of pre-programming, main erasing and post-programming, is disclosed. The method includes the steps of stopping a current step of the erasing when the suspend command appears thereat and storing a flag signal in a predetermined memory area, performing a read or programming for another sector after the stopping the current step until the resume command is applied thereto, and resuming the current step in response to an activation of the resume command.

摘要翻译： 公开了一种用于擦除布置在多个扇区中的电可擦除可编程存储单元的方法，在接收暂停命令和恢复命令的存储器件中，具有预编程，主擦除和后编程步骤的擦除。 该方法包括以下步骤：当暂停命令出现时停止擦除当前步骤，并将标志信号存储在预定的存储区域中，在停止当前步骤之后对其他扇区执行读取或编程，直到应用恢复命令 响应于恢复命令的激活而恢复当前步骤。

公开(公告)号：US08879320B2

公开(公告)日：2014-11-04

申请号：US13611598

申请日：2012-09-12

申请人： Chung-Hyun Lee ,  Ki-Hwan Choi

发明人： Chung-Hyun Lee ,  Ki-Hwan Choi

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3436

摘要： A method of programming a multi-level cells (MLC) commonly coupled to a word line in a non-volatile memory device includes shadow-programming first MLC to a first shadow state, shadow-programming second MLC to a second shadow state less than the first shadow state, and then main-programming the first MLC from the first shadow state to a first final state and main-programming the second MLC from the second shadow state to the second final state less than the first final state.

摘要翻译： 通常耦合到非易失性存储器设备中的字线的多电平单元（MLC）的编程方法包括将第一MLC的影子编程为第一影像状态，将第二影像编程第二MLC设置为小于 第一阴影状态，然后将第一MLC从第一阴影状态主编程为第一最终状态，并将第二MLC从第二阴影状态主编程为小于第一最终状态的第二最终状态。

公开(公告)号：US06233198B1

公开(公告)日：2001-05-15

申请号：US09615176

申请日：2000-07-13

申请人： Ki-Hwan Choi

发明人： Ki-Hwan Choi

IPC分类号： G11C800

CPC分类号： G11C16/08

摘要： Disclosed herein is a flash memory device that includes an improved row decoder structure. The row decoder circuit includes a row global decoder, a row partial decoder, a row local decoder, and a block decoder. The row local decoder includes drivers corresponding to local word lines. Each of the drivers includes MOS transistors to drive a corresponding local word line with a word line voltage necessary for each of the read, program, and erase operations. Since a limited number of driver transistors are utilized, the row decoding structure utilizes a smaller area in a circuit die than conventional decoding structures.

摘要翻译： 本文公开了一种闪存器件，其包括改进的行解码器结构。 行解码器电路包括行全局解码器，行部分解码器，行本地解码器和块解码器。 行本地解码器包括对应于本地字线的驱动器。 每个驱动器包括MOS晶体管，以驱动相应的本地字线与读取，编程和擦除操作中的每一个所需的字线电压。 由于利用有限数量的驱动晶体管，所以行解码结构利用电路管芯中比常规解码结构更小的面积。

公开(公告)号：US6111789A

公开(公告)日：2000-08-29

申请号：US388833

申请日：1999-09-01

申请人： Ki-Hwan Choi ,  Young-Ho Lim

发明人： Ki-Hwan Choi ,  Young-Ho Lim

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/12 ,  G11C16/34

CPC分类号： G11C16/3459 ,  G11C16/12 ,  G11C16/3454

摘要： Disclosed is a nonvolatile semiconductor memory device, operated under various modes of operation, which comprises a high voltage generating circuit, a word line voltage switching circuit, and a charge sharing circuit. The voltage switching circuit transfers to a row decoder circuit one of the various voltages corresponding to a selected mode of operation, and the charge sharing circuit is connected to an output node of the high voltage generating circuit. Further, when the memory device enters a program verify mode of operation from a program mode of operation, the charging sharing circuit lowers a word line voltage from a program voltage to a program verify voltage without charge loss, by means of charge sharing.

摘要翻译： 公开了一种在各种工作模式下工作的非易失性半导体存储器件，其包括高电压产生电路，字线电压切换电路和电荷共享电路。 电压切换电路将与选择的操作模式对应的各种电压中的一个传送到行解码器电路，并且电荷共享电路连接到高电压发生电路的输出节点。 此外，当存储器件从编程操作模式进入编程验证模式时，充电共享电路通过电荷共享将字线电压从编程电压降低到无电荷损失的程序验证电压。

公开(公告)号：US08289774B2

公开(公告)日：2012-10-16

申请号：US12414973

申请日：2009-03-31

申请人： Seung-Hyun Moon ,  Ki-Hwan Choi ,  Hyung-Gon Kim

发明人： Seung-Hyun Moon ,  Ki-Hwan Choi ,  Hyung-Gon Kim

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： Disclosed is an operating method of a flash memory device, which includes normal memory cells and dummy memory cells. The operating method includes programming the normal memory cells and programming the dummy memory cells. A dummy pass voltage used for programming the dummy memory cells is different from a normal pass voltage used for programming the normal memory cells.

摘要翻译： 公开了一种闪速存储器件的操作方法，其包括正常存储单元和虚拟存储单元。 操作方法包括对正常存储单元进行编程并编程虚拟存储单元。 用于对虚拟存储单元进行编程的虚拟通过电压与用于编程正常存储单元的正常通过电压不同。

公开(公告)号：US07366020B2

公开(公告)日：2008-04-29

申请号：US11670383

申请日：2007-02-01

申请人： Ki-Hwan Choi

发明人： Ki-Hwan Choi

IPC分类号： G11C11/34

CPC分类号： G11C16/16 ,  G11C16/344

摘要： We describe a NAND flash memory device including a memory cell array formed on a substrate including a plurality of cell strings each including a string selecting transistor, a ground selecting transistor, and plural memory cells serially coupled between the string selecting transistor and the ground selecting transistor. A high voltage generator is configured to supply a bulk voltage to the substrate and an erase control circuit is configured to stepwise increase the bulk voltage during a first period of an erase operation and to maintain the bulk voltage substantially constant during a second period of the erase operation.

摘要翻译： 我们描述了一种NAND闪速存储器件，它包括一个形成在一个衬底上的存储单元阵列，该存储单元阵列包括多个单元串，每个单元串包括串选择晶体管，接地选择晶体管和串联在串选择晶体管和接地选择晶体管之间的多个存储单元 。 高电压发生器被配置为向衬底提供体电压，并且擦除控制电路被配置为在擦除操作的第一周期期间逐步增加体电压，并且在擦除的第二周期期间保持体电压基本恒定 操作。

公开(公告)号：US07190624B2

公开(公告)日：2007-03-13

申请号：US11141732

申请日：2005-05-31

申请人： Ki-Hwan Choi

发明人： Ki-Hwan Choi

IPC分类号： C11C11/34

CPC分类号： G11C16/3418 ,  G11C16/3468 ,  G11C16/3477

摘要： The flash memory device according to the present invention includes an erase control circuit, used as a state machine, having embodied erase algorithm which can prevent flash memory cells from being over-erased. The erase control circuit, first, checks whether or not threshold voltages of selected cells reach a predetermined pre-verify voltage higher than the maximum value of a target threshold voltage range corresponding to the erased state. When at least one of the selected cells has its threshold voltage higher than the pre-verify voltage, a high voltage generator generates a bulk voltage that is increased step by step by a predetermined voltage level. And, when the selected cells all have threshold voltages equal to or less than the pre-verify voltage, the high voltage generator generates a constant bulk voltage. According to this bulk voltage control scheme, the number of flash memory cells over-erased at the erase operation is reduced reducing the total erase time.

摘要翻译： 根据本发明的闪速存储器件包括用作状态机的具有实现的擦除算法的擦除控制电路，其可以防止闪速存储器单元被过度擦除。 擦除控制电路首先检查所选择的单元的阈值电压是否达到比对应于擦除状态的目标阈值电压范围的最大值高的预定预验证电压。 当所选择的单元中的至少一个具有高于预验证电压的阈值电压时，高电压发生器产生逐步增加预定电压电平的体电压。 并且，当所选择的单元都具有等于或小于预验证电压的阈值电压时，高电压发生器产生恒定的体电压。 根据该体电压控制方案，在擦除操作时被擦除的闪存单元的数量减少，减少了总擦除时间。

公开(公告)号：US20050232022A1

公开(公告)日：2005-10-20

申请号：US11141732

申请日：2005-05-31

申请人： Ki-Hwan Choi

发明人： Ki-Hwan Choi

IPC分类号： G11C11/34 ,  G11C16/34

CPC分类号： G11C16/3418 ,  G11C16/3468 ,  G11C16/3477

摘要： The flash memory device according to the present invention includes an erase control circuit, used as a state machine, having embodied erase algorithm which can prevent flash memory cells from being over-erased. The erase control circuit, first, checks whether or not threshold voltages of selected cells reach a predetermined pre-verify voltage higher than the maximum value of a target threshold voltage range corresponding to the erased state. When at least one of the selected cells has its threshold voltage higher than the pre-verify voltage, a high voltage generator generates a bulk voltage that is increased step by step by a predetermined voltage level. And, when the selected cells all have threshold voltages equal to or less than the pre-verify voltage, the high voltage generator generates a constant bulk voltage. According to this bulk voltage control scheme, the number of flash memory cells over-erased at the erase operation is reduced reducing the total erase time.