公开(公告)号：US20200020756A1

公开(公告)日：2020-01-16

申请号：US16496969

申请日：2018-03-19

Applicant: Sharp Kabushiki Kaisha

Inventor： Teruyuki UEDA ,  Hideki KITAGAWA ,  Tohru DAITOH ,  Hajime IMAI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Tetsuo KIKUCHI ,  Toshikatsu ITOH ,  Kengo HARA

IPC: H01L27/32 ,  G02F1/1362

Abstract: An oxide semiconductor TFT (201) of an active matrix substrate includes an oxide semiconductor layer (107), an upper gate electrode (112) disposed on a part of the oxide semiconductor layer via a gate insulating layer, and a source electrode (113) and a drain electrode (114). As viewed from a normal direction of the substrate, the oxide semiconductor layer (107) includes a first portion (p1) that overlaps the upper gate electrode, and a second portion (p2) that is located between the first portion and the source contact region or drain contact region, such that the gate insulating layer does not cover the second portion. The upper gate electrode (112) has a multilayer structure including an alloy layer (112L) that is in contact with the gate insulating layer and a metal layer (112U) that is disposed on the alloy layer. The metal layer is made of a first metallic element M; the alloy layer is made of an alloy containing the first metallic element M; and the first metallic element M is Cu, Mo, or Cr.

公开(公告)号：US20230215876A1

公开(公告)日：2023-07-06

申请号：US18119624

申请日：2023-03-09

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Tetsuo KIKUCHI ,  Hideki KITAGAWA ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Hitoshi TAKAHATA ,  Tohru DAITOH

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1225

Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.

公开(公告)号：US20220246105A1

公开(公告)日：2022-08-04

申请号：US17724781

申请日：2022-04-20

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Hideki KITAGAWA ,  Hajime IMAI ,  Toshikatsu ITOH ,  Masahiko SUZUKI ,  Teruyuki UEDA ,  Kengo HARA ,  Setsuji NISHIMIYA ,  Tohru DAITOH

IPC: G09G3/36 ,  G02F1/1362 ,  H01L27/32

Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.

公开(公告)号：US20210013238A1

公开(公告)日：2021-01-14

申请号：US16919422

申请日：2020-07-02

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Yoshihito HARA ,  Tetsuo KIKUCHI ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Masamitsu YAMANAKA ,  Hitoshi TAKAHATA ,  Hajime IMAI ,  Tohru DAITOH

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368

Abstract: An active matrix substrate includes a substrate; a plurality of gate bus lines and a plurality of source bus lines; an oxide semiconductor TFT that includes an oxide semiconductor layer, a gate insulating layer, and a gate electrode; a pixel electrode; and an upper insulating layer. The oxide semiconductor layer includes a high resistance region, and a first region and a second region. The high resistance region includes a channel region, a first channel offset region, and a second channel offset region. The upper insulating layer is disposed so as to overlap the channel region, the first channel offset region, and the second channel offset region, and so as not to overlap any of the first region and the second region, when viewed from the normal direction of the main surface of the substrate.

公开(公告)号：US20200150472A1

公开(公告)日：2020-05-14

申请号：US16683726

申请日：2019-11-14

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Tohru DAITOH ,  Hajime IMAI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Kengo HARA ,  Masamitsu YAMANAKA ,  Hitoshi TAKAHATA

IPC: G02F1/1368 ,  G02F1/1362 ,  G02F1/1333

Abstract: A substrate includes thin film transistors, each of which includes: an upper gate electrode formed of a first conductive film and continuous with one of gate lines; a source electrode formed of a second conductive film and continuous with one of source lines; a channel region formed of a portion of a semiconductor film over which an upper gate insulating film is disposed and overlapping the upper gate electrode; a source region formed of a portion of the semiconductor film and continuous with the channel region, and a drain region formed of a portion of the semiconductor film and continuous with the channel region on an opposite side of the channel region from the source region. The source electrode connects the source line and the source region through a first contact hole in an interlayer insulating film disposed over the first conductive film and containing a photosensitive material.

公开(公告)号：US20200058678A1

公开(公告)日：2020-02-20

申请号：US16343024

申请日：2017-10-12

Applicant: Sharp Kabushiki Kaisha

Inventor： Teruyuki UEDA ,  Hideki KITAGAWA ,  Tohru DAITOH ,  Hajime IMAI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Tetsuo KIKUCHI ,  Toshikatsu ITOH ,  Kengo HARA

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/49 ,  H01L27/02 ,  G02F1/1368 ,  G02F1/1362

Abstract: Provided is an active matrix substrate (100A) including: a gate metal layer (15) that has a two-layer structure composed of a Cu layer (15b) and a Ti layer (15a); a first insulating layer (16) on the gate metal layer (15); a source metal layer (18) that is formed on the first insulating layer (16) and has a two-layer structure composed of a Cu layer (18b) and a Ti layer (18a); a second insulating layer (19) on the source metal layer (18); a conductive layer (25) that is formed on the second insulating layer (19), and is in contact with the gate metal layer (15) within a first opening (16a1) formed in the first insulating layer (16) and is in contact with the source metal layer (18) within a second opening (19a2) formed in the second insulating layer (19); and a first transparent conductive layer (21) that is formed on the conductive layer (25) and includes any of a pixel electrode, a common electrode and an auxiliary capacitor electrode. The conductive layer (25) does not include any of the pixel electrode, the common electrode, and the auxiliary capacitor electrode, and does not have a Ti layer being in contact with the Cu layer (15b) of the gate metal layer (15).

公开(公告)号：US20190280126A1

公开(公告)日：2019-09-12

申请号：US16293900

申请日：2019-03-06

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Masamitsu YAMANAKA ,  Tohru DAITOH ,  Hajime IMAI ,  Kengo HARA

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  G02F1/1368

Abstract: A semiconductor device includes a thin film transistor, wherein: a semiconductor layer of the thin film transistor has a layered structure including a lower oxide semiconductor layer including In, Ga, Zn and Sn and an upper oxide semiconductor layer arranged on the lower oxide semiconductor layer and including In, Ga and Zn; a thickness of the lower oxide semiconductor layer is 20 nm or less; an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer is 5% or more; the upper oxide semiconductor layer includes no Sn, or an atomic ratio of Sn with respect to all metal elements of the upper oxide semiconductor layer is smaller than an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer; and a first angle θ1 between a side surface and a lower surface of the lower oxide semiconductor layer is smaller than a second angle θ2 between a side surface and a lower surface of the upper oxide semiconductor layer.

公开(公告)号：US20170140729A1

公开(公告)日：2017-05-18

申请号：US15322802

申请日：2015-06-26

Applicant: Sharp Kabushiki Kaisha

Inventor： Toshitsugu SUEKI ,  Yasuaki IWASE ,  Takuya WATANABE ,  Akira TAGAWA ,  Kengo HARA

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28 ,  G11C19/287

Abstract: An output control node stabilization portion includes a thin film transistor having a gate terminal to which is provided a fourth clock that changes to an on level at timing at which a scanning signal outputted from a previous stage is to change from an off level to an on level, a drain terminal connected to an output control node, and a source terminal to which the scanning signal outputted from the previous stage is provided; and a thin film transistor having a gate terminal to which is provided a third clock that changes to an on level at timing at which a scanning signal outputted from a subsequent stage is to change from an off level to an on level, a drain terminal connected to the output control node, and a source terminal to which the scanning signal outputted from the subsequent stage is provided.

公开(公告)号：US20240339460A1

公开(公告)日：2024-10-10

申请号：US18746280

申请日：2024-06-18

Applicant: Sharp Kabushiki Kaisha

Inventor： Kengo HARA ,  Tohru DAITOH ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Hitoshi TAKAHATA

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L29/78633 ,  H01L29/7869

Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.

公开(公告)号：US20240297181A1

公开(公告)日：2024-09-05

申请号：US18663479

申请日：2024-05-14

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Tetsuo KIKUCHI ,  Hideki KITAGAWA ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Hitoshi TAKAHATA ,  Tohru DAITOH

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1237 ,  H01L27/127 ,  H01L29/7869 ,  H01L29/78696

Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.