公开(公告)号：US20100080074A1

公开(公告)日：2010-04-01

申请号：US12567975

申请日：2009-09-28

申请人： Takuro OHMARU ,  Tomoaki ATSUMI ,  Toshihiko SAITO

发明人： Takuro OHMARU ,  Tomoaki ATSUMI ,  Toshihiko SAITO

IPC分类号： G11C29/00

CPC分类号： G11C29/44 ,  G11C16/3459 ,  G11C16/349 ,  G11C29/4401 ,  G11C29/808 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/4402

摘要： Easy and fast memory access with correcting defects is to be realized. In a spare memory in a semiconductor memory device, a redundant memory cell array that stores the number of correcting defects is provided. When a signal from the outside is received, the signal is switched to the redundant memory cell array, and the number of correcting defects is judged. Then, based on the result of the judgment, it is determined the judgment of a defective memory cell is continued or the judgment is finished to write data to a main memory cell. By providing the redundant memory cell array that stores the number of correcting defects, a state of correcting defects can be observed fast in such a manner.

摘要翻译： 要实现具有纠正缺陷的简单快速的存储器访问。 在半导体存储器件的备用存储器中，提供存储修正缺陷数量的冗余存储单元阵列。 当接收到来自外部的信号时，信号被切换到冗余存储单元阵列，并且判断校正缺陷的数量。 然后，基于判断结果，确定不良存储单元的判断继续，或判断结束，将数据写入主存储单元。 通过提供存储校正缺陷数量的冗余存储单元阵列，可以以这种方式快速观察校正缺陷的状态。

公开(公告)号：US20120248434A1

公开(公告)日：2012-10-04

申请号：US13425674

申请日：2012-03-21

申请人： Kiyoshi KATO ,  Toshihiko SAITO

发明人： Kiyoshi KATO ,  Toshihiko SAITO

IPC分类号： H01L29/22 ,  H01L29/92

CPC分类号： H01L27/10808 ,  H01L21/84 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/1203 ,  H01L28/91

摘要： It is an object to provide a memory device where an area occupied by a memory cell is small, and moreover, a memory device where an area occupied by a memory cell is small and a data holding period is long. A memory device includes a bit line, a capacitor, a first insulating layer provided over the bit line and including a groove portion, a semiconductor layer, a second insulating layer in contact with the semiconductor layer, and a word line in contact with the second insulating layer. Part of the semiconductor layer is electrically connected to the bit line in a bottom portion of the groove portion, and another part of the semiconductor layer is electrically connected to one electrode of the capacitor in a top surface of the first insulating layer.

摘要翻译： 本发明的目的是提供一种存储器单元所占据的区域小的存储器件，而且存储器单元所占据的区域小且数据保持期间长的存储器件。 存储器件包括位线，电容器，设置在位线上并包括沟槽部分的第一绝缘层，半导体层，与半导体层接触的第二绝缘层，以及与第二绝缘层接触的字线 绝缘层。 半导体层的一部分电连接到槽部的底部的位线，半导体层的另一部分与第一绝缘层的上表面的电容器的一个电极电连接。

公开(公告)号：US20120032171A1

公开(公告)日：2012-02-09

申请号：US13193734

申请日：2011-07-29

申请人： Toshihiko SAITO ,  Yuki HATA ,  Kiyoshi KATO

发明人： Toshihiko SAITO ,  Yuki HATA ,  Kiyoshi KATO

IPC分类号： H01L27/088 ,  H01L29/786

CPC分类号： H01L27/124 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/1225 ,  H01L28/40

摘要： An object is to miniaturize a semiconductor device. Another object is to reduce the area of a driver circuit of a semiconductor device including a memory cell. The semiconductor device includes an element formation layer provided with at least a first semiconductor element, a first wiring provided over the element formation layer, an interlayer film provided over the first wiring, and a second wiring overlapping with the first wiring with the interlayer film provided therebetween. The first wiring, the interlayer film, and the second wiring are included in a second semiconductor element. The first wiring and the second wiring are wirings to which the same potentials are supplied.

摘要翻译： 目的是使半导体器件小型化。 另一个目的是减小包括存储单元的半导体器件的驱动电路的面积。 半导体器件包括至少设置有第一半导体元件的元件形成层，设置在元件形成层上的第一布线，设置在第一布线上的中间膜，和与第一布线重叠的第二布线，设置有夹层膜 之间。 第一布线，层间膜和第二布线包括在第二半导体元件中。 第一布线和第二布线是提供相同电位的布线。

公开(公告)号：US20110128801A1

公开(公告)日：2011-06-02

申请号：US13024549

申请日：2011-02-10

申请人： Toshihiko SAITO ,  Kiyoshi KATO

发明人： Toshihiko SAITO ,  Kiyoshi KATO

IPC分类号： G11C7/00

CPC分类号： H01L27/1266 ,  B82Y10/00 ,  G06K19/07749 ,  G11C13/0014 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/79 ,  H01L27/12 ,  H01L27/1214 ,  H01L51/0591

摘要： In an organic memory which is included in a radio chip formed from a thin film, data are written to the organic memory by a signal inputted with a wired connection, and the data is read with a signal by radio transmission. A bit line and a word line which form the organic memory are each selected by a signal which specifies an address generated based on the signal inputted with a wired connection. A voltage is applied to a selected memory element. Thus writing is performed. Reading is performed by a clock signal or the like which are generated from a radio signal.

摘要翻译： 在由薄膜形成的无线电芯片中包括的有机存储器中，通过用有线连接输入的信号将数据写入有机存储器，并且通过无线电传输用信号读取数据。 构成有机存储器的位线和字线各自由指定基于由有线连接输入的信号生成的地址的信号来选择。 电压被施加到选定的存储元件。 因此执行写入。 通过从无线电信号生成的时钟信号等执行读取。

公开(公告)号：US20100315868A1

公开(公告)日：2010-12-16

申请号：US12859864

申请日：2010-08-20

申请人： Hajime TOKUNAGA ,  Toshihiko SAITO

发明人： Hajime TOKUNAGA ,  Toshihiko SAITO

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： H01L27/112 ,  G11C17/16 ,  H01L21/84 ,  H01L27/105 ,  H01L27/11206 ,  H01L27/11286 ,  H01L27/12

摘要： A structure of a storage device which can operate memory elements utilizing silicide reaction using the same voltage value for writing and for reading, and a method for driving the same are proposed. The present invention relates to a storage device including a memory element and a circuit which changes a polarity of applying voltage to the memory element for writing (or reading) into a different polarity of that for reading (or writing). The memory element includes at least a first conductive layer, a film including silicon formed over the first conductive layer, and a second conductive layer formed over the silicon film. The first conductive layer and the second conductive layer of the memory element are formed using different materials.

摘要翻译： 提出了可以使用相同的写入和读取电压值来操作使用硅化物反应的存储元件的存储装置的结构及其驱动方法。 本发明涉及一种包括存储元件和电路的存储装置，该电路改变向用于写入（或写入）的不同极性的写入（或读取）存储元件的电压施加电压的极性。 存储元件至少包括第一导电层，在第一导电层上形成的包括硅的膜，以及形成在硅膜上的第二导电层。 存储元件的第一导电层和第二导电层使用不同的材料形成。