公开(公告)号：US08854191B2

公开(公告)日：2014-10-07

申请号：US11716042

申请日：2007-03-09

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Masato Ishii ,  Tomoaki Atsumi ,  Takeshi Osada ,  Takayuki Ikeda ,  Yoshiyuki Kurokawa ,  Yutaka Shionoiri

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Masato Ishii ,  Tomoaki Atsumi ,  Takeshi Osada ,  Takayuki Ikeda ,  Yoshiyuki Kurokawa ,  Yutaka Shionoiri

IPC分类号： H04Q5/22 ,  G06K19/07

CPC分类号： G06K19/0723 ,  G06K19/0701 ,  G06K19/0702

摘要： To provide a semiconductor device including an RFID which can transmit and receive individual information without checking of the remaining charge of a battery or a replacing operation of the battery in accordance with deterioration over time of the battery for driving, and can maintain an excellent state for transmission and reception of individual information even when power of a radio wave or an electromagnetic wave from outside is insufficient. A battery (also described as a secondary battery) is provided as a power supply for supplying power to the RFID. Then, when power which is obtained from a signal received from outside is larger than predetermined power, its surplus power is stored in the battery; and when the power which is obtained from the signal received from outside is smaller than the predetermined power, power which is obtained from the battery is used for the power for driving.

摘要翻译： 为了提供一种包括RFID的半导体器件，其可以根据用于驱动的​​电池的劣化随时检测电池的剩余电量或电池的替换操作而发送和接收各个信息，并且可以保持优异的状态 即使在来自外部的无线电波或电磁波的功率不足的情况下，也可以发送和接收个别信息。 提供电池（也称为二次电池）作为向RFID提供电力的电源。 然后，当从外部接收的信号获得的功率大于预定功率时，其剩余功率被存储在电池中; 并且当从外部接收的信号获得的功率小于预定功率时，从电池获得的功率用于驱动电力。

公开(公告)号：US20130069132A1

公开(公告)日：2013-03-21

申请号：US13606472

申请日：2012-09-07

申请人： Tomoaki Atsumi ,  Takashi Okuda

发明人： Tomoaki Atsumi ,  Takashi Okuda

IPC分类号： H01L27/108 ,  H01L23/485

CPC分类号： H01L27/112 ,  H01L21/76801 ,  H01L21/76826 ,  H01L27/0688 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10897 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/16 ,  H01L29/78 ,  H01L29/7869

摘要： Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked. With this structure, the memory cell array and the peripheral circuit can be shielded from radiation noise generated between the memory cell array and the peripheral circuit. Thus, probability of malfunction of the semiconductor storage device can be reduced.

摘要翻译： 减少了半导体存储装置故障的概率。 屏蔽层设置在堆叠的存储单元阵列（例如，包括使用氧化物半导体材料形成的晶体管的存储单元阵列）和周边电路（例如，包括使用半导体衬底形成的晶体管的外围电路）之间 。 利用这种结构，存储单元阵列和外围电路可以屏蔽在存储单元阵列和外围电路之间产生的辐射噪声。 因此，可以降低半导体存储装置的故障概率。

公开(公告)号：US20120275214A1

公开(公告)日：2012-11-01

申请号：US13455188

申请日：2012-04-25

申请人： Tomoaki ATSUMI ,  Yoshiya TAKEWAKI

发明人： Tomoaki ATSUMI ,  Yoshiya TAKEWAKI

IPC分类号： G11C11/24

CPC分类号： G11C5/10 ,  G11C11/401 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4099 ,  H01L27/10873 ,  H01L27/10897 ,  H01L27/1218 ,  H01L27/1225

摘要： In a memory module including a memory cell array including memory cells arranged in matrix, each including a first transistor using an oxide semiconductor and a first capacitor; a reference cell including a p-channel third transistor, a second capacitor, and a second transistor using an oxide semiconductor; and a refresh timing detection circuit including a resistor and a comparator, wherein when a potential is supplied to the first capacitor through the first transistor, a potential is supplied to the second capacitor through the second transistor, wherein a drain current value of the third transistor is changed in accordance with the potential stored in the second capacitor, and wherein when the drain current value of the third transistor is higher than a given value, a refresh operation of the memory cell array and the reference cell are performed.

摘要翻译： 在包括具有排列成矩阵的存储单元的存储单元阵列的存储器模块中，每个存储单元包括使用氧化物半导体的第一晶体管和第一电容器; 包括p沟道第三晶体管，第二电容器和使用氧化物半导体的第二晶体管的参考单元; 以及包括电阻器和比较器的刷新定时检测电路，其中当通过第一晶体管向第一电容器提供电位时，通过第二晶体管将电位提供给第二电容器，其中第三晶体管的漏极电流值 根据存储在第二电容器中的电位而改变，并且当第三晶体管的漏极电流值高于给定值时，执行存储单元阵列和参考单元的刷新操作。

公开(公告)号：US20120273773A1

公开(公告)日：2012-11-01

申请号：US13444124

申请日：2012-04-11

申请人： Yoshinori IEDA ,  Atsuo ISOBE ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI

发明人： Yoshinori IEDA ,  Atsuo ISOBE ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI

IPC分类号： H01L27/108

CPC分类号： H01L27/1207 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10805 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L28/40 ,  H01L29/04 ,  H01L29/16 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78 ,  H01L29/78648 ,  H01L29/7869

摘要： Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.

摘要翻译： 提供具有低功耗并且可以高速运行的半导体器件。 半导体器件包括：存储元件，其包括在沟道形成区域中包括晶体硅的第一晶体管，用于存储存储元件的数据的电容器;以及第二晶体管，其是用于控制电荷的供应，存储和释放的开关元件 电容器。 第二晶体管设置在覆盖第一晶体管的绝缘膜上。 第一和第二晶体管共同地具有源电极或漏电极。

公开(公告)号：US08232880B2

公开(公告)日：2012-07-31

申请号：US11716018

申请日：2007-03-09

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Masato Ishii ,  Tomoaki Atsumi ,  Takeshi Osada ,  Takayuki Ikeda ,  Yoshiyuki Kurokawa ,  Yutaka Shionoiri

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Masato Ishii ,  Tomoaki Atsumi ,  Takeshi Osada ,  Takayuki Ikeda ,  Yoshiyuki Kurokawa ,  Yutaka Shionoiri

IPC分类号： G08B13/14

CPC分类号： H01Q1/2225 ,  G06K19/0701 ,  G06K19/0702 ,  G06K19/0723 ,  G06K19/07767

摘要： The present invention provides a battery as a power supply for supplying power in the RFID, and another antenna for charging the battery, in addition to an antenna which transmits and receives individual information to and from outside as a means for supplying power to the battery.

摘要翻译： 本发明提供一种作为用于在RFID中供电的电源的电池，以及用于对电池充电的另一个天线，以及向外部发送和接收个人信息的天线作为向电池供电的装置。

公开(公告)号：US20110315780A1

公开(公告)日：2011-12-29

申请号：US13226770

申请日：2011-09-07

申请人： Tomoaki ATSUMI ,  Yutaka SHIONOIRI ,  Hidetomo KOBAYASHI

发明人： Tomoaki ATSUMI ,  Yutaka SHIONOIRI ,  Hidetomo KOBAYASHI

IPC分类号： G06K19/073

CPC分类号： G06K19/07749 ,  G06K19/0708

摘要： Initialization of a semiconductor device can be efficiently performed, which transmits and receives data through wireless communication. The semiconductor device includes an antenna, a power source circuit, a circuit which uses a DC voltage generated by the power source circuit as a power source voltage, and a resistor. The antenna includes a pair of terminals and receives a wireless signal (a modulated carrier wave). The power source circuit includes a first terminal and a second terminal and generates a DC voltage between the first terminal and the second terminal by using a received wireless signal (the modulated carrier wave). The resistor is connected between the first terminal and the second terminal. In this manner, the semiconductor device and the wireless communication system can transmit and receive data accurately.

摘要翻译： 可以有效地执行半导体器件的初始化，其通过无线通信发送和接收数据。 半导体器件包括天线，电源电路，使用由电源电路产生的直流电压作为电源电压的电路和电阻器。 天线包括一对终端，并接收无线信号（调制载波）。 电源电路包括第一端子和第二端子，并且通过使用接收的无线信号（调制载波）在第一端子和第二端子之间产生直流电压。 电阻器连接在第一端子和第二端子之间。 以这种方式，半导体器件和无线通信系统可以准确地发送和接收数据。

公开(公告)号：US20100163631A1

公开(公告)日：2010-07-01

申请号：US12645082

申请日：2009-12-22

申请人： Masato Ishii ,  Tomoaki Atsumi

发明人： Masato Ishii ,  Tomoaki Atsumi

IPC分类号： G06K19/07 ,  G06K7/01

CPC分类号： G06K19/0723 ,  G06K19/0701 ,  H01L28/10

摘要： A semiconductor device capable of wireless communication which has low power consumption in a step for decoding an encoded signal to obtain data is provided. The semiconductor device includes an antenna configured to convert received carrier waves into an AC signal, a rectifier circuit configured to rectify the AC signal into a DC voltage, a demodulation circuit configured to demodulate the AC signal into an encoded signal, an oscillator circuit configured to generate a clock signal having a certain frequency by supply of the DC voltage, a synchronizing circuit configured to generate a synchronized encoded signal by synchronizing the encoded signal obtained by demodulating the AC signal with the clock signal, a decoder circuit configured to decode the synchronized encoded signal into a decoded signal, and a register configured to store the decoded signal as a clock (referred to as a digital signal).

摘要翻译： 提供了一种能够在用于解码编码信号以获得数据的步骤中具有低功耗的无线通信的半导体器件。 该半导体装置包括将接收的载波转换为交流信号的天线，被配置为将交流信号整流为直流电压的整流电路，被配置为将该交流信号解调为编码信号的解调电路， 通过提供DC电压产生具有一定频率的时钟信号;同步电路，被配置为通过将通过解调AC信号获得的编码信号与时钟信号同步来生成同步编码信号;解码器电路，被配置为对同步编码的 信号转换为解码信号，以及配置为将解码信号存储为时钟（称为数字信号）的寄存器。

公开(公告)号：US07518592B2

公开(公告)日：2009-04-14

申请号：US11622510

申请日：2007-01-12

申请人： Jun Koyama ,  Tomoaki Atsumi ,  Hiroyuki Miyake

发明人： Jun Koyama ,  Tomoaki Atsumi ,  Hiroyuki Miyake

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0809 ,  G09G2300/0828 ,  G09G2300/0842 ,  G09G2300/0857

摘要： A liquid crystal display device with low power consumption is provided. In the liquid crystal display device having a source signal line driver circuit, a gate signal line driver circuit, a DAC controller, and a pixel portion and performing an image display using an n-bit (n is a natural number, n≧2) digital image signal, one pixel has memory circuits for storing an n-bit digital image signal and a D/A converter, and the n-bit digital image signal for one frame can be stored in the pixel. In case of a static image display, the image signal stored in the memory circuits is read out every frame to perform the display, and thus, only a DAC controller is driven during the display. Therefore, this contributes to a reduction of the power consumption of the entire liquid crystal display device.

公开(公告)号：US07352604B2

公开(公告)日：2008-04-01

申请号：US11607053

申请日：2006-12-01

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G11C17/00

CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/12

摘要： According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.

摘要翻译： 根据本发明，通过减少元件的数量来减小安装面积并提高产量，并且提供了对外围电路的负担较小的存储器及其驱动方法。 本发明包括一个存储单元，其中存储单元包括位线和字线与插在它们之间的绝缘体交叉的区域中的存储元件，列解码器和包括时钟反相器的选择器。 时钟反相器的输入节点连接到位线，而输出节点连接到数据线。 在形成时钟反相器的串联连接的多个晶体管中，源极或漏极连接到高电位侧VDD上的电源的P型晶体管的栅极和N型晶体管的栅极 源极或漏极连接到低电位侧的电源VSS连接到列解码器。

公开(公告)号：US09318374B2

公开(公告)日：2016-04-19

申请号：US13606472

申请日：2012-09-07

申请人： Tomoaki Atsumi ,  Takashi Okuda

发明人： Tomoaki Atsumi ,  Takashi Okuda

IPC分类号： H01L21/768 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  H01L27/115

CPC分类号： H01L27/112 ,  H01L21/76801 ,  H01L21/76826 ,  H01L27/0688 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10897 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/16 ,  H01L29/78 ,  H01L29/7869

摘要： Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked. With this structure, the memory cell array and the peripheral circuit can be shielded from radiation noise generated between the memory cell array and the peripheral circuit. Thus, probability of malfunction of the semiconductor storage device can be reduced.

摘要翻译： 减少了半导体存储装置故障的概率。 屏蔽层设置在堆叠的存储单元阵列（例如，包括使用氧化物半导体材料形成的晶体管的存储单元阵列）和周边电路（例如，包括使用半导体衬底形成的晶体管的外围电路）之间 。 利用这种结构，存储单元阵列和外围电路可以屏蔽在存储单元阵列和外围电路之间产生的辐射噪声。 因此，可以降低半导体存储装置的故障概率。