公开(公告)号：US06486515B2

公开(公告)日：2002-11-26

申请号：US10131536

申请日：2002-04-24

申请人： Song Jun ,  Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek

发明人： Song Jun ,  Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek

IPC分类号： H01L2362

CPC分类号： H01L27/0251 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. An N-well is formed within a silicon semiconductor substrate. A P+ region is implanted within a portion of the N-well and an N+ region is implanted within a portion of the semiconductor substrate not occupied by the N-well. An oxide layer is formed overlying the semiconductor substrate and patterned to form openings to the semiconductor substrate. An epitaxial silicon layer is grown within the openings and overlying the oxide layer. Shallow trench isolation regions are formed within the epitaxial silicon layer extending to the underlying oxide layer. Gate electrodes and associated source and drain regions are formed in and on the epitaxial silicon layer between the shallow trench isolation regions. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. The interlevel dielectric layer is covered with a mask that covers the first contact openings. Second contact openings are opened through the interlevel dielectric layer, shallow trench isolations, and the oxide layer to the N+ region and P+ region. The mask is removed. The first and second contact openings are filled with a conducting layer to complete formation of an ESD device.

摘要翻译： 描述了使用绝缘体上硅技术形成静电放电装置的方法。 在硅半导体衬底内形成N阱。 将P +区注入到N阱的一部分内，并且将N +区注入到不被N阱占据的半导体衬底的一部分内。 在半导体衬底上形成氧化物层并图案化以形成到半导体衬底的开口。 外延硅层生长在开口内并覆盖氧化物层。 在延伸到下面的氧化物层的外延硅层内形成浅沟槽隔离区。 在浅沟槽隔离区域之间的外延硅层中和栅极电极和相关的源极和漏极区域上形成栅电极。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 用覆盖第一接触开口的掩模覆盖层间电介质层。 第二接触开口通过层间介质层，浅沟槽隔离层和氧化物层开放到N +区域和P +区域。 去除面具。 第一和第二接触开口填充有导电层以完成ESD装置的形成。

公开(公告)号：US06399431B1

公开(公告)日：2002-06-04

申请号：US09531786

申请日：2000-03-21

申请人： Jun Song ,  Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong

发明人： Jun Song ,  Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong

IPC分类号： H01L2170

CPC分类号： H01L21/84 ,  H01L27/0266 ,  H01L27/1203 ,  H01L29/78603

摘要： A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. A silicon-on-insulator substrate is provided comprising a semiconductor substrate underlying an oxide layer underlying a silicon layer. The silicon layer and oxide layer are patterned to form a gate electrode wherein the semiconductor substrate is exposed. Ions are implanted into the exposed semiconductor substrate to form source and drain regions adjacent to the gate electrode. Spacers are formed on sidewalls of the gate electrode. An interlevel dielectric layer is deposited overlying the gate electrode. Openings are formed through the interlevel dielectric layer to the source and drain regions and filled with a conducting layer. The conducting layer is patterned to form conducting lines to complete formation of an electrostatic discharge device using SOI technology in the fabrication of integrated circuits.

摘要翻译： 描述了使用绝缘体上硅技术形成静电放电装置的方法。 提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下方的半导体衬底。 图案化硅层和氧化物层以形成其中暴露半导体衬底的栅电极。 将离子注入到暴露的半导体衬底中以形成与栅电极相邻的源区和漏区。 隔板形成在栅电极的侧壁上。 沉积在栅电极上的层间电介质层。 开口通过层间介电层形成到源区和漏区，并填充有导电层。 图案化导电层以形成导线，以在集成电路的制造中使用SOI技术完成静电放电装置的形成。

公开(公告)号：US06376379B1

公开(公告)日：2002-04-23

申请号：US09495344

申请日：2000-02-01

申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Song ,  Sang Yee Loong

发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Song ,  Sang Yee Loong

IPC分类号： H01L21302

CPC分类号： H01L21/31144 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76829

摘要： A method of patterning a hard mask, the comprising the following steps. A semiconductor structure is provided. A conductor film is formed over the semiconductor structure. An oxide layer is formed over the conductor film. A patterned metal oxide layer is formed over the conductor film. The oxide layer and the conductor film are etched, using the metal oxide layer as a hard mask, to form a patterned structure.

摘要翻译： 图案化硬掩模的方法，包括以下步骤。 提供半导体结构。 在半导体结构上形成导体膜。 在导体膜上形成氧化物层。 在导体膜上形成图案化的金属氧化物层。 使用金属氧化物层作为硬掩模来蚀刻氧化物层和导体膜，以形成图案化结构。

公开(公告)号：US06492242B1

公开(公告)日：2002-12-10

申请号：US09609447

申请日：2000-07-03

申请人： Alex See ,  Cher Liang Randall Cha ,  Shyuz Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

发明人： Alex See ,  Cher Liang Randall Cha ,  Shyuz Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

IPC分类号： H01L2120

CPC分类号： H01L28/40 ,  H01L21/31683

摘要： A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures. A second iteration features the exposure of specific regions of an underlying metal layer, to a UV, or to an I line exposure procedure, performed in an oxidizing ambient, with the regions of an underlying metal layer exposed to the UV or I line procedure, via clear regions in an overlying photolithographic plate. This procedure also results in the formation of a high K layer, on a top portion of the underlying metal layer.

摘要翻译： 在高于周围结构所经历的温度的温度下进行的金属氧化物 - 金属电容器结构的高介电常数（高K）层，其特征在于底层金属层的局部氧化， 已经开发 该方法的第一次迭代的特征在于在氧化环境中使用对底层金属层的局部区域进行的激光烧蚀程序。 激光烧蚀过程仅在激光点产生所需的高温，允许在该温度下产生高K层，而不直接暴露于激光烧蚀过程的半导体衬底上的周围结构保持在较低温度 。 第二次迭代的特征在于在氧化环境中进行的底层金属层的特定区域到UV或I线曝光程序，暴露于UV或I线程序的下面的金属层的区域， 通过覆盖光刻板中的透明区域。 该过程还导致在下面的金属层的顶部上形成高K层。

公开(公告)号：US06300172B1

公开(公告)日：2001-10-09

申请号：US09409887

申请日：1999-10-01

申请人： Ting Cheong Ang ,  Shyue Pong Quek ,  Lap Chan ,  Sang Yee Loong

发明人： Ting Cheong Ang ,  Shyue Pong Quek ,  Lap Chan ,  Sang Yee Loong

IPC分类号： H01L2100

CPC分类号： H01L21/76264 ,  H01L21/76281

摘要： A method of fabricating an SOI transistor device comprises the following steps. a silicon semiconductor structure is provided. A silicon oxide layer is formed over the silicon semiconductor structure. A silicon-on-insulator layer is formed over the oxide layer. A well is implanted in the silicon-on-insulator layer. A gate oxide layer is grown over the silicon-on-insulator layer. A polysilicon layer is deposited over the gate oxide layer. The polysilicon layer, gate oxide layer, and silicon oxide layer are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised shallow trench isolation regions (STIs). The polysilicon layer is patterned and the non-gate portions are removed polysilicon adjacent the raised STIs forming a gate conductor between the raised STIs with the gate conductor and said raised STIs having exposed sidewalls. The gate oxide layer is removed between the gate conductor and the raised STIs, and outboard of the raised STIs. The source and drain are formed in the silicon-on-insulator layer adjacent the gate spacers. Silicide regions may then be formed on the source and drain.

摘要翻译： 制造SOI晶体管器件的方法包括以下步骤。 提供硅半导体结构。 在硅半导体结构上形成氧化硅层。 在氧化物层上形成绝缘体上硅层。 将阱注入绝缘体上硅层中。 栅氧化层生长在绝缘体上硅层上。 在栅极氧化物层上沉积多晶硅层。 对多晶硅层，栅极氧化物层和氧化硅层进行图案化和蚀刻以形成沟槽。 沟槽用隔离材料填充至少甚至具有多晶硅层的顶表面的水平以形成凸起的浅沟槽隔离区域（STI）。 多晶硅层被图案化，并且非栅极部分去除与凸起的STI相邻的多晶硅，其在栅极导体和所述凸起的STI具有暴露的侧壁之间在凸起的STI之间形成栅极导体。 栅极氧化物层在栅极导体和凸起的STI之间以及凸起的STIs的外侧被移除。 源极和漏极形成在邻近栅极间隔物的绝缘体上硅层中。 然后可以在源极和漏极上形成硅化物区域。

公开(公告)号：US6110787A

公开(公告)日：2000-08-29

申请号：US391886

申请日：1999-09-07

申请人： Lap Chan ,  Ting Cheong Ang ,  Shyue Pong Quek ,  Sang Yee Loong

发明人： Lap Chan ,  Ting Cheong Ang ,  Shyue Pong Quek ,  Sang Yee Loong

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/41775 ,  H01L21/76224 ,  H01L29/41783 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/78

摘要： A method of fabricating a MOS device having raised source/drain, raised isolation regions having isolation spacers, and a gate conductor having gate spacers is achieved. A layer of gate silicon oxide is grown over the surface of a semiconductor structure. A polysilicon layer is deposited overlying the gate silicon oxide layer. The polysilicon layer, gate silicon oxide layer and semiconductor structure are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised isolation regions. The remaining polysilicon layer is patterned to remove polysilicon adjacent the raised isolation regions forming a gate conductor between the raised isolation regions. The gate conductor and the raised isolation regions having exposed sidewalls. The gate oxide layer between the gate conductor and raised isolation regions is removed. Isolation spacers are formed on the exposed sidewalls of the raised isolation regions and gate spacers are formed on the exposed sidewalls of the gate conductor. A layer of silicon is deposited and patterned to form raised source and drain adjacent the gate spacers with source and drain being doped to form a MOS device.

摘要翻译： 实现了具有升高的源极/漏极，具有隔离间隔物的升高的隔离区域以及具有栅极间隔物的栅极导体的MOS器件的制造方法。 在半导体结构的表面上生长栅极氧化硅层。 沉积覆盖栅氧化硅层的多晶硅层。 对多晶硅层，栅极氧化硅层和半导体结构进行图案化和蚀刻以形成沟槽。 沟槽用隔离材料填充至少甚至具有多晶硅层的顶表面的水平以形成凸起的隔离区域。 将剩余的多晶硅层图案化以去除在凸起的隔离区域之间形成栅极导体的凸起的隔离区域附近的多晶硅。 栅极导体和凸起的隔离区域具有暴露的侧壁。 去除栅极导体与升高隔离区之间的栅极氧化层。 在凸起的隔离区域的暴露的侧壁上形成绝缘间隔物，并且栅极间隔物形成在栅极导体的暴露的侧壁上。 沉积一层硅并图案化以形成与栅极间隔物相邻的凸起源极和漏极，源极和漏极被掺杂以形成MOS器件。

公开(公告)号：US20090250818A1

公开(公告)日：2009-10-08

申请号：US12486521

申请日：2009-06-17

申请人： Bei Chao Zhang ,  Chun Hui Low ,  Hong Lim Lee ,  Sang Yee Loong ,  Qiang Guo

发明人： Bei Chao Zhang ,  Chun Hui Low ,  Hong Lim Lee ,  Sang Yee Loong ,  Qiang Guo

IPC分类号： H01L23/522

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76814

摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

摘要翻译： 描述了一种用于提高半导体器件中的电迁移阻力的集成方法。 在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。 一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。 在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。 另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。 发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。

公开(公告)号：US07781895B2

公开(公告)日：2010-08-24

申请号：US12486521

申请日：2009-06-17

申请人： Bei Chao Zhang ,  Chun Hui Low ,  Hong Lim Lee ,  Sang Yee Loong ,  Qiang Guo

发明人： Bei Chao Zhang ,  Chun Hui Low ,  Hong Lim Lee ,  Sang Yee Loong ,  Qiang Guo

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76814

摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

公开(公告)号：US07691739B2

公开(公告)日：2010-04-06

申请号：US11374848

申请日：2006-03-13

申请人： Bei Chao Zhang ,  Chun Hui Low ,  Hong Lim Lee ,  Sang Yee Loong ,  Qiang Guo

发明人： Bei Chao Zhang ,  Chun Hui Low ,  Hong Lim Lee ,  Sang Yee Loong ,  Qiang Guo

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76814

摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

摘要翻译： 描述了一种用于提高半导体器件中的电迁移阻力的集成方法。 在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。 一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。 在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。 另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。 发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。

公开(公告)号：US07045455B2

公开(公告)日：2006-05-16

申请号：US10692028

申请日：2003-10-23

申请人： Beichao Zhang ,  Chun Hui Low ,  Hong Lim Lee ,  Sang Yee Loong ,  Qiang Guo

发明人： Beichao Zhang ,  Chun Hui Low ,  Hong Lim Lee ,  Sang Yee Loong ,  Qiang Guo

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76814

摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

摘要翻译： 描述了一种用于提高半导体器件中的电迁移阻力的集成方法。 在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。 一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。 在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。 另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。 发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。