公开(公告)号：US11467962B2

公开(公告)日：2022-10-11

申请号：US17009876

申请日：2020-09-02

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Wesley Waylon Terpstra ,  Henry Cook ,  Leigang Kou

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0846 ,  G06F12/0891 ,  G06F12/123

Abstract: Described are methods and a system for atomic memory operations with contended cache lines. A processing system includes at least two cores, each core having a local cache, and a lower level cache in communication with each local cache. One local cache configured to request a cache line to execute an atomic memory operation (AMO) instruction, receive the cache line via the lower level cache, receive a probe downgrade due to other local cache requesting the cache line prior to execution of the AMO, and send the AMO instruction to the lower level cache for remote execution in response to the probe downgrade.

公开(公告)号：US11442856B2

公开(公告)日：2022-09-13

申请号：US17103856

申请日：2020-11-24

Applicant: SiFive, Inc.

Inventor： Wesley Waylon Terpstra

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/02 ,  G06F12/0846 ,  G06F12/0882

Abstract: Systems and methods are disclosed for virtualized caches. For example, an integrated circuit (e.g., a processor) for executing instructions includes a virtually indexed physically tagged first-level (L1) cache configured to output to an outer memory system one or more bits of a virtual index of a cache access as one or more bits of a requestor identifier. For example, the L1 cache may be configured to operate as multiple logical L1 caches with a cache way of a size less than or equal to a virtual memory page size. For example, the integrated circuit may include an L2 cache of the outer memory system that is configured to receive the requestor identifier and implement a cache coherency protocol to disambiguate an L1 synonym occurring in multiple portions of the virtually indexed physically tagged L1 cache associated with different requestor identifier values.

公开(公告)号：US20220066936A1

公开(公告)日：2022-03-03

申请号：US17009876

申请日：2020-09-02

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Wesley Waylon Terpstra ,  Henry Cook ,  Leigang Kou

IPC: G06F12/0811 ,  G06F12/0891 ,  G06F12/0846 ,  G06F12/0813 ,  G06F12/123

Abstract: Described are methods and a system for atomic memory operations with contended cache lines. A processing system includes at least two cores, each core having a local cache, and a lower level cache in communication with each local cache. One local cache configured to request a cache line to execute an atomic memory operation (AMO) instruction, receive the cache line via the lower level cache, receive a probe downgrade due to other local cache requesting the cache line prior to execution of the AMO, and send the AMO instruction to the lower level cache for remote execution in response to the probe downgrade.

公开(公告)号：US11151301B2

公开(公告)日：2021-10-19

申请号：US16851966

申请日：2020-04-17

Applicant: SiFive, Inc.

Inventor： Megan Wachs ,  Henry Cook ,  Wesley Waylon Terpstra

IPC: G06F30/398 ,  G06F30/333

Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with point-to-point connections between modules. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. For example, type parameterization may be used to generate point-to-point connections in a flexible manner. For example, a point-to-point connection between the source module and the sink module that includes one or more named wires specified by bundle type may be automatically generated based on using the bundle type as a type parameterization input. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

公开(公告)号：US20210286724A1

公开(公告)日：2021-09-16

申请号：US17332286

申请日：2021-05-27

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Wesley Waylon Terpstra ,  Henry Cook

IPC: G06F12/0804 ,  G06F12/128

Abstract: Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.

公开(公告)号：US20240232083A1

公开(公告)日：2024-07-11

申请号：US18406128

申请日：2024-01-06

Applicant: SiFive, Inc.

Inventor： Wesley Waylon Terpstra ,  Richard Van ,  Chao Wei Huang ,  Kevin Heuer

IPC: G06F12/0811 ,  G06F12/123

CPC classification number: G06F12/0811 ,  G06F12/123

Abstract: Systems and methods are disclosed for partitioning a cache for application of a replacement policy. For example, some methods may include partitioning entries of a set in a cache into two or more subsets; receiving a message that will cause a cache block replacement; responsive to the message, selecting a way of the cache by applying a replacement policy to entries of the cache from only a first subset of the two or more subsets; and responsive to the message, evicting an entry of the cache in the first subset and in the selected way.

公开(公告)号：US20240184721A1

公开(公告)日：2024-06-06

申请号：US18133022

申请日：2023-04-11

Applicant: SiFive, Inc.

Inventor： Eric Andrew Gouldey ,  Michael Klinglesmith ,  Henry Cook ,  Wesley Waylon Terpstra

IPC: G06F13/16

CPC classification number: G06F13/1626

Abstract: A method for managing orders of operations between one or more clients and one or more servers is disclosed. The method includes partitioning addressable regions of logical servers on or within an interconnect link into multiple regions including a first orderable region, and providing logical client an ability to push ordering responsibility within the first orderable region to a server. Over the first orderable region, two request messages for access to memory-mapped sources including two respective operations are transmitted, and the two request messages originate from a same logical client. The ordering responsibility can include a first rule for order of operations between the two request messages.

公开(公告)号：US20240184720A1

公开(公告)日：2024-06-06

申请号：US18341093

申请日：2023-06-26

Applicant: SiFive, Inc.

Inventor： Michael Klinglesmith ,  Eric Andrew Gouldey ,  Wesley Waylon Terpstra

IPC: G06F13/16 ,  G06F12/084 ,  G06F13/42

CPC classification number: G06F13/1621 ,  G06F12/084 ,  G06F13/4234

Abstract: First agent circuitry may receive from a second agent a first request and a first set of one or more bits. The first request may be part of a data operation. The first agent circuitry may transmit to the second agent a message including a first response to the first request, the first set of one or more bits, a second request, and a second set of one or more bits. The second set of one or more bits may be generated by the first agent circuitry to transmit state information about the second request. In some implementations, a set of one or more wires may be generated for transmission of the second set of one or more bits. The first agent circuitry may receive from the second agent a second response to the second request and the second set of one or more bits.

公开(公告)号：US20240184718A1

公开(公告)日：2024-06-06

申请号：US18132572

申请日：2023-04-10

Applicant: SiFive, Inc.

Inventor： Michael Klinglesmith ,  Eric Andrew Gouldey ,  Wesley Waylon Terpstra

IPC: G06F12/14

CPC classification number: G06F12/1458 ,  G06F2212/1052

Abstract: Cache circuitry may be configured to receive a first message to downgrade a permission associated with data stored in a current level cache. For example, the current level cache could be a level two (L2) cache. The cache circuitry could receive the first message from a processor core having a level one (L1) cache. The cache circuitry may forward the first message to a higher level cache. For example, the higher level cache could be a level three (L3) cache. The cache circuitry may downgrade the permission associated with data stored in the current level cache based on receiving a second message from the higher level cache. The cache circuitry may forward the first message before receiving the second message and downgrading the permission. The second message may cause downgrade of the permission in multiple caches (e.g., the L1, L2, and L3 caches).

公开(公告)号：US20240184702A1

公开(公告)日：2024-06-06

申请号：US18182778

申请日：2023-03-13

Applicant: SiFive, Inc.

Inventor： Eric Andrew Gouldey ,  Wesley Waylon Terpstra ,  Michael Klinglesmith

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/1024

Abstract: Prefetch circuitry may be configured to transmit a message to prefetch one or more cache blocks of a group. The message may indicate an address for the group of cache blocks and a bit field that indicates the one or more cache blocks of the group to prefetch. In some implementations, the message may target a higher level cache to prefetch the one or more cache blocks, and the message may be transmitted to the higher level cache via a lower level cache. In some implementations, the message may target a higher level cache to prefetch the one or more cache blocks, the message may be transmitted to a lower level cache via a first command bus, and the lower level cache may forward the message to the higher level cache via a second command bus.