公开(公告)号：US20060267696A1

公开(公告)日：2006-11-30

申请号：US11496421

申请日：2006-08-01

Applicant: Siavash Fallahi ,  Chun Chen ,  Mark Chambers

Inventor： Siavash Fallahi ,  Chun Chen ,  Mark Chambers

IPC: H03L7/00

CPC classification number: H03L7/18 ,  G11B20/1403 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/0996 ,  H03L7/0998

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

公开(公告)号：US07005899B2

公开(公告)日：2006-02-28

申请号：US11062495

申请日：2005-02-23

Applicant: Siavash Fallahi ,  Myles Wakayama ,  Pieter Vorenkamp

Inventor： Siavash Fallahi ,  Myles Wakayama ,  Pieter Vorenkamp

IPC: H03K23/00

CPC classification number: H03L7/081 ,  H03K23/68 ,  H03L7/0996 ,  H03L7/18

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract translation: 一种方法和系统，用于通过任何非整数输出信号频率相对于锁相环（PLL）的参考信号频率进行倍频/除法，同时保持低抖动。 在一个实施例中，本发明将可用时钟相位的数目增加到M，然后每K / M周期将输出时钟相位移位1。 在本发明的一个方面，这通过将多路复用器（MUX）添加到PLL的输出端来实现，以实现每K / M个周期的相移。 在另一方面，MUX被放置在PLL的反馈回路中。 在一个实施例中，使用量化器来驱动MUX。

公开(公告)号：US20050140411A1

公开(公告)日：2005-06-30

申请号：US11062495

申请日：2005-02-23

Applicant: Siavash Fallahi ,  Myles Wakayama ,  Pieter Vorenkamp

Inventor： Siavash Fallahi ,  Myles Wakayama ,  Pieter Vorenkamp

IPC: H03K23/68 ,  H03L7/081 ,  H03L7/099 ,  H03L7/18 ,  H03K3/00

CPC classification number: H03L7/081 ,  H03K23/68 ,  H03L7/0996 ,  H03L7/18

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

公开(公告)号：US06888405B2

公开(公告)日：2005-05-03

申请号：US10372778

申请日：2003-02-26

Applicant: Felix Cheung ,  Kevin T. Chan ,  Siavash Fallahi

Inventor： Felix Cheung ,  Kevin T. Chan ,  Siavash Fallahi

IPC: H03G1/00 ,  H03F1/36

CPC classification number: H03G1/0088

Abstract: A programable gain amplifier (PGA) has an amplifier and a variable resistor that is connected to the output of the amplifier. The variable resistor includes a resistor that is connected to a reference voltage and multiple parallel taps that tap off the resistor. A two-stage switch network having fine stage switches and coarse stage switches connects the resistor taps to an output node of the PGA. The taps and corresponding fine stage switches are arranged into two or more groups, where each group has n-number of fine stage switches and corresponding taps. One terminal of each fine stage switch is connected to the corresponding resistor tap, and the other terminal is connected to an output terminal for the corresponding group. The coarse stage switches select from among the groups of fine stage switches, and connect to the output of the PGA. During operation, one selected tap is connected to the output of the PGA by closing the appropriate fine stage switch and coarse stage switch, where the selected tap defines a selected group of the fine stage switches. Additionally, one fine stage switch is closed in each of the non-selected groups of fine stage switches. In one embodiment, the location of the closed switches in the non-selected groups is the mirror image of the location in an adjacent group. This reduces the transient voltages that occur when tap selection changes from one group to another.

公开(公告)号：US06441655B1

公开(公告)日：2002-08-27

申请号：US09736612

申请日：2000-12-14

Applicant: Siavash Fallahi ,  Myles Wakayama ,  Pieter Vorenkamp

Inventor： Siavash Fallahi ,  Myles Wakayama ,  Pieter Vorenkamp

IPC: H03K2300

CPC classification number: H03L7/081 ,  H03K23/68 ,  H03L7/0996 ,  H03L7/18

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase-Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract translation: 一种方法和系统，用于通过任何非整数输出信号频率相对于锁相环（PLL）的参考信号频率进行倍频/除法，同时保持低抖动。 在一个实施例中，本发明将可用时钟相位的数目增加到M，然后每K / M周期将输出时钟相位移位1。 在本发明的一个方面，这通过将多路复用器（MUX）添加到PLL的输出端来实现，以实现每K / M个周期的相移。 在另一方面，MUX被放置在PLL的反馈回路中。 在一个实施例中，使用量化器来驱动MUX。

公开(公告)号：US08977869B2

公开(公告)日：2015-03-10

申请号：US13037462

申请日：2011-03-01

Applicant: Jingguang Wang ,  Derek Tam ,  Mark Berman ,  Siavash Fallahi

Inventor： Jingguang Wang ,  Derek Tam ,  Mark Berman ,  Siavash Fallahi

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3206

Abstract: While an IC chip is in idle mode with no power being supplied to the IC chip, the IC chip may be operable to detect a signal pulse received by the IC chip using energy associated with the signal pulse. The IC chip may be operable to control a control signal for a power switch using the energy associated with the signal pulse. The power switch may allow power to be provided to the IC chip based on the control signal. The IC chip may comprise a pulse detector, a latch circuit and an ON/OFF logic circuit within the IC chip. While the IC chip is fully powered and communication with a partner chip is finished, the IC chip may be operable to control the control signal to turn off the power switch for powering down the IC chip based on a turn-off signal.

Abstract translation: 虽然IC芯片处于空闲模式，而没有向IC芯片提供电力，但是IC芯片可以用于使用与信号脉冲相关联的能量来检测由IC芯片接收的信号脉冲。 IC芯片可以用于使用与信号脉冲相关联的能量来控制功率开关的控制信号。 电源开关可以基于控制信号来允许向IC芯片提供电力。 IC芯片可以包括IC芯片内的脉冲检测器，锁存电路和ON / OFF逻辑电路。 当IC芯片完全供电并且与伙伴芯片的通信完成时，IC芯片可以可操作地控制控制信号以关闭电源开关，以基于关断信号对IC芯片供电。

公开(公告)号：US07414410B2

公开(公告)日：2008-08-19

申请号：US11513213

申请日：2006-08-31

Applicant: Art Pharn ,  Peiqing Wang ,  Siavash Fallahi

Inventor： Art Pharn ,  Peiqing Wang ,  Siavash Fallahi

IPC: G01R31/02 ,  G01R31/11

CPC classification number: G01R31/11

Abstract: A system and method are used to determine connectivity and/or cable faults of a cable. A signal transmitting and receiving system is coupled to the cable. An analog-to-digital converter (ADC) coupled to the signal transmitting and receiving system. A TDR system coupled to the ADC and a memory, and a controlling system coupled to at least one of the ADC, the TDR system, and the signal receiving and transmitting system. The controlling system includes a controller and one or more state machines that are used to control the TDR system.

Abstract translation: 使用系统和方法来确定电缆的连接和/或电缆故障。 信号发射和接收系统耦合到电缆。 耦合到信号发射和接收系统的模拟 - 数字转换器（ADC）。 耦合到ADC和存储器的TDR系统以及耦合到ADC，TDR系统和信号接收和传输系统中的至少一个的控制系统。 控制系统包括控制器和用于控制TDR系统的一个或多个状态机。

公开(公告)号：US07274260B2

公开(公告)日：2007-09-25

申请号：US11496421

申请日：2006-08-01

Applicant: Siavash Fallahi ,  Chun Ying Chen ,  Mark J. Chambers

Inventor： Siavash Fallahi ,  Chun Ying Chen ,  Mark J. Chambers

IPC: H03L7/00

CPC classification number: H03L7/18 ,  G11B20/1403 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/0996 ,  H03L7/0998

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

Abstract translation: 一种用于产生具有用于接收参考信号的输入端的多个合成时钟的系统，耦合到所述输入信号端的锁相环电路，其中所述锁相环电路能够产生频率锁定到所述输入信号的多个输出信号 参考信号并且具有多个不同的相位，耦合到锁相环电路的相位旋转器，其中相位旋转器产生更大的多个相位。

公开(公告)号：US07164274B2

公开(公告)日：2007-01-16

申请号：US10855621

申请日：2004-05-28

Applicant: Art Pharn ,  Peiqing Wang ,  Siavash Fallahi

Inventor： Art Pharn ,  Peiqing Wang ,  Siavash Fallahi

IPC: G01R31/02 ,  G01R31/11

CPC classification number: G01R31/11

Abstract: A system and method are used to determine connectivity and/or cable faults of a cable. A signal transmitting and receiving system is coupled to the cable. An analog-to-digital converter (ADC) coupled to the signal transmitting and receiving system. A TDR system coupled to the ADC and a memory, and a controlling system coupled to at least one of the ADC, the TDR system, and the signal receiving and transmitting system.

Abstract translation: 系统和方法用于确定电缆的连接和/或电缆故障。 信号发射和接收系统耦合到电缆。 耦合到信号发射和接收系统的模拟 - 数字转换器（ADC）。 耦合到ADC和存储器的TDR系统以及耦合到ADC，TDR系统和信号接收和传输系统中的至少一个的控制系统。

公开(公告)号：US07106071B2

公开(公告)日：2006-09-12

申请号：US10855622

申请日：2004-05-28

Applicant: Art Pharn ,  Peiqing Wang ,  Siavash Fallahi

Inventor： Art Pharn ,  Peiqing Wang ,  Siavash Fallahi

IPC: G01R31/02 ,  G01R31/11

CPC classification number: G01R31/11

Abstract: A system and method are used to determine connectivity and/or cable faults of a cable. A signal transmitting and receiving system is coupled to the cable. An analog-to-digital converter (ADC) coupled to the signal transmitting and receiving system. A TDR system coupled to the ADC and a memory, and a controlling system coupled to at least one of the ADC, the TDR system, and the signal receiving and transmitting system. The controlling system includes a controller and one or more state machines that are used to control the TDR system.

Abstract translation: 系统和方法用于确定电缆的连接和/或电缆故障。 信号发射和接收系统耦合到电缆。 耦合到信号发射和接收系统的模拟 - 数字转换器（ADC）。 耦合到ADC和存储器的TDR系统以及耦合到ADC，TDR系统和信号接收和传输系统中的至少一个的控制系统。 控制系统包括控制器和用于控制TDR系统的一个或多个状态机。