公开(公告)号：US06630288B2

公开(公告)日：2003-10-07

申请号：US09819342

申请日：2001-03-28

申请人： Jeffrey A. Shields ,  Uzodinma Okoroanyanwu ,  Chih-Yuh Yang

发明人： Jeffrey A. Shields ,  Uzodinma Okoroanyanwu ,  Chih-Yuh Yang

IPC分类号： G03F700

CPC分类号： H01L21/28123 ,  H01L21/32139 ,  Y10S430/143

摘要： A process for forming sub-lithographic features in an integrated circuit is disclosed herein. The process includes modifying a photoresist layer after patterning and development but before it is utilized to pattern the underlying layers. The modified photoresist layer has different etch rates in the vertical and horizontal directions. The modified photoresist layer is trimmed with a plasma etch. A feature included in the trimmed photoresist layer has a sub-lithographic lateral dimension.

公开(公告)号：US06200884B1

公开(公告)日：2001-03-13

申请号：US09364976

申请日：1999-07-31

申请人： Chih-Yuh Yang ,  Mark S. Chang

发明人： Chih-Yuh Yang ,  Mark S. Chang

IPC分类号： H01L21425

CPC分类号： H01L21/0274 ,  H01L21/266 ,  H01L21/31138

摘要： A method for making a ULSI MOSFET chip includes masking areas such as transistor gates with photoresist mask regions. Prior to ion implantation, the top shoulders of the mask regions are etched away, to round off the shoulders. This promotes subsequent efficient quasi-vertical ion implantation, commonly referred to as “high aspect ratio implantation” in the semiconductor industry.

摘要翻译： 制造ULSI MOSFET芯片的方法包括具有光致抗蚀剂掩模区域的诸如晶体管栅极的掩模区域。 在离子注入之前，掩模区域的顶部肩部被蚀刻掉，从而使肩部圆整。 这促进随后的有效的准垂直离子注入，在半导体工业中通常被称为“高纵横比植入”。

公开(公告)号：US6060377A

公开(公告)日：2000-05-09

申请号：US306874

申请日：1999-05-07

申请人： Qi Xiang ,  Scott A. Bell ,  Chih-Yuh Yang

发明人： Qi Xiang ,  Scott A. Bell ,  Chih-Yuh Yang

IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L21/32139 ,  H01L21/0338 ,  H01L21/28123 ,  H01L29/6659

摘要： A polysilicon structure is fabricated with a reduced length that is beyond that achievable from photolithography by using a silicidation anneal to control the reduced length. Generally, the present invention includes a step of forming a masking polysilicon structure having a first predetermined length defined by sidewalls on ends of the first predetermined length of the masking polysilicon structure. The present invention also includes a step of depositing a layer of metal on the sidewalls of the masking polysilicon structure. The layer of metal has a predetermined thickness. The layer of metal reacts with the masking polysilicon structure at the sidewalls of the masking polysilicon structure in a silicidation anneal to form metal silicide. The masking polysilicon structure has a second predetermined length that is reduced from the first predetermined length when the metal silicide has consumed into the sidewalls of the masking polysilicon structure after the silicidation anneal. The second predetermined length depends on the predetermined thickness of the layer of metal deposited on the sidewalls of the masking polysilicon structure. The masking polysilicon structure has the second predetermined length and is used as a mask for etching a first layer of polysilicon to form the polysilicon structure from the first layer of polysilicon. The remaining polysilicon structure after this etch has the reduced length that is substantially equal to the second predetermined length of the masking polysilicon structure. The present invention may be used to particular advantage when the polysilicon structure having the reduced length forms a gate electrode of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

摘要翻译： 通过使用硅化退火来控制缩短的长度，制造出具有减小的长度的多晶硅结构，其超过通过光刻实现的结果。 通常，本发明包括形成具有由掩模多晶硅结构的第一预定长度的端部上的侧壁限定的第一预定长度的掩模多晶硅结构的步骤。 本发明还包括在掩模多晶硅结构的侧壁上沉积金属层的步骤。 金属层具有预定的厚度。 金属层在硅化退火中在掩模多晶硅结构的侧壁处与掩模多晶硅结构反应以形成金属硅化物。 掩模多晶硅结构具有第二预定长度，当在硅化退火之后金属硅化物消耗到掩模多晶硅结构的侧壁时，该第二预定长度从第一预定长度减小。 第二预定长度取决于沉积在掩模多晶硅结构的侧壁上的金属层的预定厚度。 掩模多晶硅结构具有第二预定长度，并且用作蚀刻第一多晶硅层的掩模，以从第一多晶硅层形成多晶硅结构。 在该蚀刻之后的剩余多晶硅结构具有基本上等于掩模多晶硅结构的第二预定长度的减小的长度。 当具有减小的长度的多晶硅结构形成MOSFET（金属氧化物半导体场效应晶体管）的栅电极时，本发明可以特别有利。

公开(公告)号：US07696038B1

公开(公告)日：2010-04-13

申请号：US11412365

申请日：2006-04-26

申请人： Ning Cheng ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita ,  Timothy Thurgate ,  Wei Zheng ,  Ashot Melik-Martirosian ,  Angela Hui ,  Chih-Yuh Yang

发明人： Ning Cheng ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita ,  Timothy Thurgate ,  Wei Zheng ,  Ashot Melik-Martirosian ,  Angela Hui ,  Chih-Yuh Yang

IPC分类号： H01L21/8238

CPC分类号： H01L27/11568 ,  G11C16/3418 ,  G11C16/3427

摘要： Methods for fabricating flash memory devices are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises forming a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack. A first impurity doped region is formed within the substrate underlying the trench.

摘要翻译： 提供了制造闪速存储器件的方法。 根据本发明的示例性实施例，一种用于制造存储器件的方法包括形成覆盖衬底的第一栅极堆叠和第二栅极堆叠。 在第一栅极堆叠和第二栅极堆叠之间的沟槽被蚀刻到衬底中。 第一杂质掺杂区域形成在沟槽下面的衬底内。

公开(公告)号：US07675104B2

公开(公告)日：2010-03-09

申请号：US11461131

申请日：2006-07-31

申请人： Amol Ramesh Joshi ,  Harpreet Sachar ,  YouSeok Suh ,  Shenqing Fang ,  Chih-Yuh Yang ,  Lovejeet Singh ,  David H. Matsumoto ,  Hidehiko Shiraiwa ,  Kuo-Tung Chang ,  Scott A. Bell ,  Allison Holbrook ,  Satoshi Torii

发明人： Amol Ramesh Joshi ,  Harpreet Sachar ,  YouSeok Suh ,  Shenqing Fang ,  Chih-Yuh Yang ,  Lovejeet Singh ,  David H. Matsumoto ,  Hidehiko Shiraiwa ,  Kuo-Tung Chang ,  Scott A. Bell ,  Allison Holbrook ,  Satoshi Torii

IPC分类号： H01L21/8247

CPC分类号： H01L27/11568 ,  H01L21/3081 ,  H01L21/76224 ,  H01L27/115 ,  H01L29/66833

摘要： An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.

摘要翻译： 一种集成电路存储器系统，包括：提供衬底; 在所述衬底上形成富硅电荷存储层; 通过富硅电荷存储层沿第一方向形成第一隔离沟槽; 以及在第二方向上通过富硅电荷存储层形成第二隔离沟槽。

公开(公告)号：US06764966B1

公开(公告)日：2004-07-20

申请号：US10085278

申请日：2002-02-27

申请人： William George En ,  Arvind Halliyal ,  Ming-Ren Lin ,  Minh Van Ngo ,  Chih-Yuh Yang

发明人： William George En ,  Arvind Halliyal ,  Ming-Ren Lin ,  Minh Van Ngo ,  Chih-Yuh Yang

IPC分类号： H01L2128

CPC分类号： H01L29/6656 ,  H01L29/66833 ,  H01L29/78

摘要： A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a dielectric layer interposed between a gate electrode and the semiconductor substrate. Further, the semiconductor device includes graded dielectric constant spacers formed on sidewalls of the dielectric layer, sidewalls of the gate electrode and portions of an upper surface of the semiconductor substrate. The dielectric constant of the graded dielectric constant spacers decreases in a direction away from the sidewalls of the dielectric layer.

摘要翻译： 公开了一种形成在具有有源区的半导体衬底上的半导体器件及其制造方法。 半导体器件包括插入在栅电极和半导体衬底之间的电介质层。 此外，半导体器件包括形成在电介质层的侧壁，栅电极的侧壁和半导体衬底的上表面的部分上的渐变介电常数间隔物。 梯度介电常数间隔物的介电常数在远离介电层的侧壁的方向上减小。

公开(公告)号：US06653231B2

公开(公告)日：2003-11-25

申请号：US09819344

申请日：2001-03-28

申请人： Uzodinma Okoroanyanwu ,  Chih-Yuh Yang ,  Jeffrey A. Shields

发明人： Uzodinma Okoroanyanwu ,  Chih-Yuh Yang ,  Jeffrey A. Shields

IPC分类号： H01L2144

CPC分类号： H01L21/32139 ,  H01L21/28123 ,  H01L22/20

摘要： A process for forming sub-lithographic features in an integrated circuit is disclosed herein. A process for enhancing the etch trimmability and the etch stability of features patterned on a photoresist layer is also disclosed herein. The process includes curing a photoresist layer after patterning and development but before an etch process is performed thereon. By controlling the formation of the cured portions of the features patterned on the photoresist layer, the features can be trimmed to sub-lithographic critical dimensions without pattern deformation or occurrence of other failure mechanisms.

公开(公告)号：US06589709B1

公开(公告)日：2003-07-08

申请号：US09819692

申请日：2001-03-28

申请人： Uzodinma Okoroanyanwu ,  Jeffrey A. Shields ,  Chih-Yuh Yang

发明人： Uzodinma Okoroanyanwu ,  Jeffrey A. Shields ,  Chih-Yuh Yang

IPC分类号： G03F700

CPC分类号： H01L21/28123

摘要： A process for preventing deformation of patterned photoresist features during integrated circuit fabrication is disclosed herein. The process includes stabilizing the patterned photoresist features by a flood electron beam before one or more etch processes. The stabilized patterned photoresist features resist pattern bending, breaking, collapsing, or deforming during a given etch process. The electron beam stabilization can be applied to the patterned photoresist features a plurality of times as desired.

摘要翻译： 本文公开了在集成电路制造期间防止图案化光致抗蚀剂特征变形的方法。 该方法包括在一个或多个蚀刻工艺之前通过泛洪电子束稳定图案化的光致抗蚀剂特征。 稳定的图案化光刻胶特征在给定的蚀刻工艺期间抵抗图案弯曲，断裂，塌陷或变形。 电子束稳定可根据需要多次施加到图案化的光致抗蚀剂特征。

公开(公告)号：US06323093B1

公开(公告)日：2001-11-27

申请号：US09290088

申请日：1999-04-12

申请人： Qi Xiang ,  Scott Allan Bell ,  Chih-Yuh Yang

发明人： Qi Xiang ,  Scott Allan Bell ,  Chih-Yuh Yang

IPC分类号： H01L21336

CPC分类号： H01L21/28123

摘要： A process for fabricating a semiconductor device includes the formation of a hard-mask using lithographic techniques, followed by an oxidation process to reduce the lateral dimension of the hard-mask. The oxidation process is carried out by selectively oxidizing an oxidizable layer overlying an etch-stop layer. Upon completion of the oxidation process, the etch-stop layer is removed and a residual layer of oxidizable material is then used as a mask for the formation of a device component. The lateral dimension of the residual layer can be substantially less than that achievable by optical lithographic techniques.

摘要翻译： 制造半导体器件的方法包括使用光刻技术形成硬掩模，随后进行氧化处理以减小硬掩模的横向尺寸。 通过选择性地氧化覆盖在蚀刻停止层上的可氧化层来进行氧化过程。 氧化工艺完成后，去除蚀刻停止层，然后使用剩余的可氧化材料层作为形成器件部件的掩模。 残余层的横向尺寸可以显着小于通过光学平版印刷技术实现的尺寸。

公开(公告)号：US06211044B1

公开(公告)日：2001-04-03

申请号：US09290087

申请日：1999-04-12

申请人： Qi Xiang ,  Scott Allan Bell ,  Chih-Yuh Yang

发明人： Qi Xiang ,  Scott Allan Bell ,  Chih-Yuh Yang

IPC分类号： H01L213205

CPC分类号： H01L21/28123 ,  H01L29/6659

摘要： A process for fabricating a semiconductor device includes the formation of a hard-mask using lithographic techniques followed by a selective silicidation reaction process to reduce the lateral dimension of the hard-mask. The silicidation reaction is carried out by selectively reacting a reaction layer situated between an etch-stop layer and a reaction resistant layer. Upon completion of the chemical reaction process, the etch-stop layer and the reaction resistant layer is removed, and a residual layer of unreacted material is then used as a mask for the formation of a device component. The lateral dimension of the residual layer can be substantially less than that achievable by optical lithographic techniques.

摘要翻译： 制造半导体器件的方法包括使用光刻技术形成硬掩膜，然后进行选择性硅化反应工艺以减小硬掩模的横向尺寸。 通过选择性地使位于蚀刻停止层和反应层之间的反应层反应来进行硅化反应。 化学反应过程完成后，除去蚀刻停止层和反应层，然后使用残留的未反应材料层作为形成器件组分的掩模。 残余层的横向尺寸可以显着小于通过光学平版印刷技术实现的尺寸。