公开(公告)号：US6060377A

公开(公告)日：2000-05-09

申请号：US306874

申请日：1999-05-07

申请人： Qi Xiang ,  Scott A. Bell ,  Chih-Yuh Yang

发明人： Qi Xiang ,  Scott A. Bell ,  Chih-Yuh Yang

IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L21/32139 ,  H01L21/0338 ,  H01L21/28123 ,  H01L29/6659

摘要： A polysilicon structure is fabricated with a reduced length that is beyond that achievable from photolithography by using a silicidation anneal to control the reduced length. Generally, the present invention includes a step of forming a masking polysilicon structure having a first predetermined length defined by sidewalls on ends of the first predetermined length of the masking polysilicon structure. The present invention also includes a step of depositing a layer of metal on the sidewalls of the masking polysilicon structure. The layer of metal has a predetermined thickness. The layer of metal reacts with the masking polysilicon structure at the sidewalls of the masking polysilicon structure in a silicidation anneal to form metal silicide. The masking polysilicon structure has a second predetermined length that is reduced from the first predetermined length when the metal silicide has consumed into the sidewalls of the masking polysilicon structure after the silicidation anneal. The second predetermined length depends on the predetermined thickness of the layer of metal deposited on the sidewalls of the masking polysilicon structure. The masking polysilicon structure has the second predetermined length and is used as a mask for etching a first layer of polysilicon to form the polysilicon structure from the first layer of polysilicon. The remaining polysilicon structure after this etch has the reduced length that is substantially equal to the second predetermined length of the masking polysilicon structure. The present invention may be used to particular advantage when the polysilicon structure having the reduced length forms a gate electrode of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

摘要翻译： 通过使用硅化退火来控制缩短的长度，制造出具有减小的长度的多晶硅结构，其超过通过光刻实现的结果。 通常，本发明包括形成具有由掩模多晶硅结构的第一预定长度的端部上的侧壁限定的第一预定长度的掩模多晶硅结构的步骤。 本发明还包括在掩模多晶硅结构的侧壁上沉积金属层的步骤。 金属层具有预定的厚度。 金属层在硅化退火中在掩模多晶硅结构的侧壁处与掩模多晶硅结构反应以形成金属硅化物。 掩模多晶硅结构具有第二预定长度，当在硅化退火之后金属硅化物消耗到掩模多晶硅结构的侧壁时，该第二预定长度从第一预定长度减小。 第二预定长度取决于沉积在掩模多晶硅结构的侧壁上的金属层的预定厚度。 掩模多晶硅结构具有第二预定长度，并且用作蚀刻第一多晶硅层的掩模，以从第一多晶硅层形成多晶硅结构。 在该蚀刻之后的剩余多晶硅结构具有基本上等于掩模多晶硅结构的第二预定长度的减小的长度。 当具有减小的长度的多晶硅结构形成MOSFET（金属氧化物半导体场效应晶体管）的栅电极时，本发明可以特别有利。

公开(公告)号：US6133129A

公开(公告)日：2000-10-17

申请号：US306875

申请日：1999-05-07

申请人： Qi Xiang ,  Scott A. Bell ,  Chih-Yuh Yang

发明人： Qi Xiang ,  Scott A. Bell ,  Chih-Yuh Yang

IPC分类号： H01L21/28 ,  H01L21/321 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L21/28123 ,  H01L21/28079 ,  H01L21/321 ,  H01L29/66575 ,  Y10S438/947

摘要： A metal structure is fabricated with a reduced length that is beyond that achievable from photolithography by using a silicidation anneal to control the reduced length. Generally, the present invention includes a step of forming a base metal structure on a semiconductor substrate. The base metal structure has a first predetermined length defined by sidewalls on ends of the first predetermined length of the base metal structure. The present invention also includes the step of depositing a layer of silicon on the sidewalls of the base metal structure, and this layer of silicon has a predetermined thickness. The layer of silicon reacts with the base metal structure at the sidewalls of the base metal structure in a silicidation anneal to form metal silicide comprised of the layer of silicon that has reacted with the base metal structure at the sidewalls of the base metal structure. The base metal structure has a second predetermined length that is reduced from the first predetermined length when the layer of silicon has consumed into the sidewalls of the base metal structure after the silicidation anneal. The second predetermined length depends on the predetermined thickness of the layer of silicon deposited on the sidewalls of the base metal structure before the silicidation anneal. After the silicidation anneal, the metal silicide is then removed from the sidewalls of the base metal structure. A remaining portion of the base metal structure, after the metal silicide is removed, forms the metal structure of the present invention having the reduced length that is substantially equal to the second predetermined length. The present invention may be used to particular advantage when the metal structure having the reduced length forms a gate electrode of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

摘要翻译： 通过使用硅化退火来控制缩短的长度，制造出具有减小的长度的金属结构，其超过了通过光刻可以实现的结构。 通常，本发明包括在半导体衬底上形成贱金属结构的步骤。 贱金属结构具有由基体金属结构的第一预定长度的端部上的侧壁限定的第一预定长度。 本发明还包括在基底金属结构的侧壁上沉积硅层的步骤，并且该硅层具有预定的厚度。 硅层在贱金属结构的侧壁处与基体金属结构反应，以在硅化退火中形成金属硅化物，该金属硅化物由在贱金属结构的侧壁处与基体金属结构反应的硅层组成。 贱金属结构具有第二预定长度，当硅层在硅化退火之后消耗到基体金属结构的侧壁中时，该第一预定长度从第一预定长度减小。 第二预定长度取决于在硅化退火之前沉积在贱金属结构的侧壁上的硅层的预定厚度。 在硅化退火之后，然后从基体金属结构的侧壁去除金属硅化物。 在金属硅化物被除去之后，母体金属结构的剩余部分形成具有基本上等于第二预定长度的减小的长度的本发明的金属结构。 当具有减小的长度的金属结构形成MOSFET（金属氧化物半导体场效应晶体管）的栅电极时，本发明可以被用于特别的优点。

公开(公告)号：US06287918B1

公开(公告)日：2001-09-11

申请号：US09290086

申请日：1999-04-12

申请人： Qi Xiang ,  Scott Allan Bell ,  Chih-Yuh Yang

发明人： Qi Xiang ,  Scott Allan Bell ,  Chih-Yuh Yang

IPC分类号： H01L21336

CPC分类号： H01L21/28079 ,  H01L21/28123 ,  H01L21/31683

摘要： A process for fabricating a semiconductor device includes the formation of a metal device feature layer using lithographic techniques, followed by an oxidation process to reduce the lateral dimension of the metal device feature. The oxidation process is carried out by selectively, laterally oxidizing the metal composition of the device feature that overlies a dielectric layer. The lateral oxidation process forms metal oxide sidewall spacers on the device feature. Upon completion of the oxidation process, the metal oxide sidewall spacers are removed and a residual layer of unoxidized metal remains. The lateral dimension of the residual layer can be substantially less than that achievable by optical lithographic techniques.

摘要翻译： 制造半导体器件的方法包括使用光刻技术形成金属器件特征层，随后进行氧化处理以减小金属器件特征的横向尺寸。 通过选择性地横向氧化覆盖在电介质层上的器件特征的金属组合物进行氧化过程。 横向氧化工艺在器件特征上形成金属氧化物侧壁间隔物。 氧化工艺完成后，去除金属氧化物侧壁间隔物，剩下残留的未氧化金属层。 残余层的横向尺寸可以显着小于通过光学平版印刷技术实现的尺寸。

公开(公告)号：US06214683B1

公开(公告)日：2001-04-10

申请号：US09290555

申请日：1999-04-12

申请人： Qi Xiang ,  Scott Allan Bell ,  Chih-Yuh Yang

发明人： Qi Xiang ,  Scott Allan Bell ,  Chih-Yuh Yang

IPC分类号： H01L21336

CPC分类号： H01L21/28123 ,  H01L21/32139 ,  H01L29/665

摘要： A process for fabricating a semiconductor device includes the formation of a hard-mask using lithographic techniques followed by a lateral oxidation process to reduce the lateral dimension of the hard-mask. The lateral oxidation is carried out by selectively oxidizing an oxidizable layer situated between an etch-stop layer and an oxidation resistant layer. Upon completion of the lateral oxidation process, etch-stop layer and the oxidation resistant are removed and a residual layer of oxidizable material is then used as a mask for the formation of a device component. The lateral dimension of the residual layer can be substantially less than that achievable by optical lithographic techniques.

摘要翻译： 制造半导体器件的方法包括使用光刻技术形成硬掩膜，然后进行横向氧化处理以减小硬掩模的横向尺寸。 侧向氧化通过选择性地氧化位于蚀刻停止层和抗氧化层之间的可氧化层来进行。 在完成横向氧化工艺后，去除蚀刻停止层和耐氧化层，然后使用剩余的可氧化材料层作为用于形成器件部件的掩模。 残余层的横向尺寸可以显着小于通过光学平版印刷技术实现的尺寸。

公开(公告)号：US6121155A

公开(公告)日：2000-09-19

申请号：US205590

申请日：1998-12-04

申请人： Chih-Yuh Yang ,  Scott Bell ,  Qi Xiang

发明人： Chih-Yuh Yang ,  Scott Bell ,  Qi Xiang

IPC分类号： H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/302

CPC分类号： H01L21/82385 ,  H01L21/3088 ,  H01L21/31116

摘要： The present invention provides a process for self-limiting trim etch of patterned photoresist that will allow integrated circuit fabrication to achieve smaller integrated circuit component features and greatly reduce final critical dimension drift or variation. Trim time is set in a plateau region of the critical dimension loss process curve.

摘要翻译： 本发明提供了一种用于图案化光致抗蚀剂的自限制微调蚀刻的方法，其将允许集成电路制造实现更小的集成电路组件特征并大大减少最终临界尺寸漂移或变化。 修剪时间设置在临界尺寸损失过程曲线的平台区域。

公开(公告)号：US06323093B1

公开(公告)日：2001-11-27

申请号：US09290088

申请日：1999-04-12

申请人： Qi Xiang ,  Scott Allan Bell ,  Chih-Yuh Yang

发明人： Qi Xiang ,  Scott Allan Bell ,  Chih-Yuh Yang

IPC分类号： H01L21336

CPC分类号： H01L21/28123

摘要： A process for fabricating a semiconductor device includes the formation of a hard-mask using lithographic techniques, followed by an oxidation process to reduce the lateral dimension of the hard-mask. The oxidation process is carried out by selectively oxidizing an oxidizable layer overlying an etch-stop layer. Upon completion of the oxidation process, the etch-stop layer is removed and a residual layer of oxidizable material is then used as a mask for the formation of a device component. The lateral dimension of the residual layer can be substantially less than that achievable by optical lithographic techniques.

摘要翻译： 制造半导体器件的方法包括使用光刻技术形成硬掩模，随后进行氧化处理以减小硬掩模的横向尺寸。 通过选择性地氧化覆盖在蚀刻停止层上的可氧化层来进行氧化过程。 氧化工艺完成后，去除蚀刻停止层，然后使用剩余的可氧化材料层作为形成器件部件的掩模。 残余层的横向尺寸可以显着小于通过光学平版印刷技术实现的尺寸。

公开(公告)号：US06211044B1

公开(公告)日：2001-04-03

申请号：US09290087

申请日：1999-04-12

申请人： Qi Xiang ,  Scott Allan Bell ,  Chih-Yuh Yang

发明人： Qi Xiang ,  Scott Allan Bell ,  Chih-Yuh Yang

IPC分类号： H01L213205

CPC分类号： H01L21/28123 ,  H01L29/6659

摘要： A process for fabricating a semiconductor device includes the formation of a hard-mask using lithographic techniques followed by a selective silicidation reaction process to reduce the lateral dimension of the hard-mask. The silicidation reaction is carried out by selectively reacting a reaction layer situated between an etch-stop layer and a reaction resistant layer. Upon completion of the chemical reaction process, the etch-stop layer and the reaction resistant layer is removed, and a residual layer of unreacted material is then used as a mask for the formation of a device component. The lateral dimension of the residual layer can be substantially less than that achievable by optical lithographic techniques.

摘要翻译： 制造半导体器件的方法包括使用光刻技术形成硬掩膜，然后进行选择性硅化反应工艺以减小硬掩模的横向尺寸。 通过选择性地使位于蚀刻停止层和反应层之间的反应层反应来进行硅化反应。 化学反应过程完成后，除去蚀刻停止层和反应层，然后使用残留的未反应材料层作为形成器件组分的掩模。 残余层的横向尺寸可以显着小于通过光学平版印刷技术实现的尺寸。

公开(公告)号：US08502283B2

公开(公告)日：2013-08-06

申请号：US11926655

申请日：2007-10-29

申请人： Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

发明人： Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC分类号： H01L29/78

CPC分类号： H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

摘要翻译： 提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。 形成深沟槽隔离，向半导体层引入应变。 栅极电介质和栅极形成在半导体层上。 在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。 凹陷的源极/漏极形成在间隔物外部。

公开(公告)号：US08482963B1

公开(公告)日：2013-07-09

申请号：US12629831

申请日：2009-12-02

申请人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

发明人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

摘要翻译： 不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。 也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。 可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。 两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。 两个晶体管的栅极也连接在一起。 两个晶体管可以具有不同的阈值电压。 位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。 堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。 不对称晶体管也可用于存储器单元中以减少泄漏。

公开(公告)号：US07923785B2

公开(公告)日：2011-04-12

申请号：US10643461

申请日：2003-08-18

申请人： Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

发明人： Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

IPC分类号： H01L21/336

CPC分类号： H01L29/4983 ,  H01L29/02 ,  H01L29/4925 ,  H01L29/513 ,  H01L29/78 ,  H01L29/7845 ,  Y10S438/938

摘要： According to one exemplary embodiment, a FET which is situated over a substrate, comprises a channel situated in the substrate. The FET further comprises a first gate dielectric situated over the channel, where the first gate dielectric has a first coefficient of thermal expansion. The FET further comprises a first gate electrode situated over the first gate dielectric, where the first gate electrode has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel.

摘要翻译： 根据一个示例性实施例，位于衬底上方的FET包括位于衬底中的通道。 FET还包括位于沟道上方的第一栅极电介质，其中第一栅极电介质具有第一热膨胀系数。 FET还包括位于第一栅极电介质上方的第一栅电极，其中第一栅电极具有第二热膨胀系数，并且其中第二热膨胀系数不同于第一热膨胀系数，从而导致 增加FET中的载流子迁移率。 例如，第二热膨胀系数可以大于第一热膨胀系数。 载流子迁移率的增加可以由例如在通道中产生的拉伸应变引起。