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21.发明授权Frame stripping protocol for early token release in a ring communication network 失效在环通信网络中的早期令牌释放的帧去除协议
公开(公告)号：US4932023A
公开(公告)日：1990-06-05
申请号：US368739
申请日：1989-06-20
IPC分类号： H04L12/433
CPC分类号： H04L12/433
摘要： A frame stripping algorithm for use in a ring communication network utilizing early token release wherein multiple frames can exist on the ring at one time. The algorithm introduces two new strip terminating conditions which supplement two of the three conditions applicable to a normal token release scheme. The first of these conditions occurs when the source address in a received message is not the same as the receiving station's address and no code violation errors have been detected. The second condition occurs when the receiving station detects an isolated ending delimiter without a preceding starting delimiter.
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22.发明申请STRUCTURE FOR ONE-SAMPLE-PER-BIT DECISION FEEDBACK EQUALIZER (DFE) CLOCK AND DATA RECOVERY 审中-公开一次性决策反馈均衡器（DFE）时钟和数据恢复的结构公开(公告)号：US20080240224A1
公开(公告)日：2008-10-02
申请号：US12138214
申请日：2008-06-12
申请人： JUAN A. CARBALLO , Hayden C. Cranford , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
发明人： JUAN A. CARBALLO , Hayden C. Cranford , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H04L27/01
CPC分类号： H04L25/03885 , H04L25/03057 , H04L2025/03356
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER) is provided. The design generally includes a receiver circuit. The receiver circuit generally includes a decision feedback equalizer (DFE) that produces one sample per bit, and means for automatically self-adjusting the DFE to enable an eye centering process by which peak energy is maintained within the receiver circuit when phase error is a minimum.
摘要翻译： 一种体现在机器可读存储介质中的设计结构，用于设计，制造和/或测试利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的设计 提供接收机并降低误码率（BER）。 该设计通常包括接收器电路。 接收器电路通常包括每位产生一个采样的判决反馈均衡器（DFE），以及用于自动自调整DFE的装置，以便当相位误差最小时能够在接收器电路内保持峰值能量的眼睛对中过程 。
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公开(公告)号：US20080133164A1
公开(公告)日：2008-06-05
申请号：US12021950
申请日：2008-01-29
CPC分类号： G01R31/31901 , G01R31/31707
摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.
摘要翻译： 公开了一种用于测试高速电路的方法和系统。 该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。 该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。 因此，可以确定高速电路是否在期望的参数内起作用。
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公开(公告)号：US07315594B2
公开(公告)日：2008-01-01
申请号：US10484608
申请日：2002-07-15
IPC分类号： H04L7/00
CPC分类号： H03L7/091 , H03L7/0814 , H03L7/089 , H04L7/0331
摘要： The invention is directed to a clock data recovery system for resampling a clock signal to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependant on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.
摘要翻译： 本发明涉及一种用于将时钟信号重新采样到输入数据信号的时钟数据恢复系统。 时钟数据恢复系统包括用于产生时钟信号的时钟发生器和用于根据相位调整控制信号产生采样相位的相位调整单元。 它还包括可操作以产生输入样本流的数据采样单元和用于从其产生内部早期信号和内部迟滞信号的边缘检测器。 设置相位调整控制单元，用于在早期信号的使用下产生相位调整控制信号，并且延迟信号。 相位调整控制单元可以用外部早/晚信号进给，和/或包括用于传送出口早/晚信号的输出。
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25.发明授权Method and system for providing quality control on wafers running on a manufacturing line 失效用于对在生产线上运行的晶片提供质量控制的方法和系统公开(公告)号：US07089132B2
公开(公告)日：2006-08-08
申请号：US10709805
申请日：2004-05-28
CPC分类号： G01R31/2831 , H01L22/14
摘要： A method for providing quality control on wafers running on a manufacturing line is disclosed. The resistances on a group of manufacturing test structures within a wafer running on a wafer manufacturing line are initially measured. Then, an actual distribution value is obtained based on the result of the measured resistances on the group of manufacturing test structures. The difference between the actual distribution value and a predetermined distribution value is recorded. Next, the resistances on a group of design test structures within the wafer are measured. The measured resistances of the group of design test structures are correlated to the measured resistances of the group of manufacturing test structures in order to obtain an offset value. The resistance of an adjustable resistor circuit within the wafer and subsequent wafers running on the wafer manufacturing line are adjusted according to the offset value.
摘要翻译： 公开了一种用于对在生产线上运行的晶片进行质量控制的方法。 初始测量在晶片生产线上运行的晶片内的一组制造测试结构的电阻。 然后，基于制造试验结构体的测定电阻的结果，求出实际的分布值。 记录实际分布值与预定分布值之间的差。 接下来，测量晶片内的一组设计测试结构的电阻。 设计测试结构组的测量电阻与制造测试结构组的测量电阻相关，以获得偏移值。 根据偏移值调整晶片内的可调节电阻电路和在晶片生产线上运行的随后的晶片的电阻。
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公开(公告)号：US4748588A
公开(公告)日：1988-05-31
申请号：US810139
申请日：1985-12-18
CPC分类号： H04J3/062
摘要： A circuit arrangement for synchronizing source data from a source system with a clock and/or clocks from a sink system. The circuit arrangement includes a source counter, a buffer, a sink counter and a controller. The source data is placed in consecutive buffer positions under the control of the source counter. The sink counter is made to "follow" the source counter and identifies the location in the buffer whereat output data is to be extracted. The controller monitors the counters and generates control signals representative of the state of the buffer.
摘要翻译： 用于使来自源系统的源数据与来自sink系统的时钟和/或时钟同步的电路装置。 电路装置包括源计数器，缓冲器，汇计数器和控制器。 源数据位于源计数器控制下的连续缓冲位置。 宿计数器用于“跟踪”源计数器，并标识要在其中提取输出数据的缓冲器中的位置。 控制器监视计数器并产生代表缓冲器状态的控制信号。
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公开(公告)号：US20080150599A1
公开(公告)日：2008-06-26
申请号：US11828390
申请日：2007-07-26
IPC分类号： H03K3/84
CPC分类号： H04L25/068 , H04B3/462 , H04L1/205
摘要： Apparatuses and methods comprise a phase shifter, an adjustable capacitance configured to adjust a phase shift of said phase shifter, an arbitrary waveform generator configured to adjust the adjustable capacitance, and a pulse pattern generator coupled to the phase shifter, the phase shifter is configured to control the pulse pattern generator. In one aspect, an adjustable capacitance is at least one varactor diode. In another, a pair of varactor diodes are separated by λ/4 lines, an input and an output of the adjustable capacitance is AC-coupled, and the arbitrary waveform generator is configured to adjust the adjustable capacitance through a gaussian noise signal input to the pair of varactor diodes. A deterministic jitter generator may be coupled to the pulse pattern generator. An open-circuited stub line may be input to the pattern generator, a deterministic jitter content number adjustable varying stub line length.
摘要翻译： 装置和方法包括移相器，被配置为调整所述移相器的相移的可调电容，被配置为调节可调电容的任意波形发生器以及耦合到移相器的脉冲图形发生器，所述移相器被配置为 控制脉冲模式发生器。 在一个方面，可调电容是至少一个变容二极管。 另一方面，一对变容二极管由λ/ 4线分开，可调电容的输入和输出是交流耦合的，并且任意波形发生器被配置成通过高斯噪声信号输入到 一对变容二极管。 确定性抖动发生器可以耦合到脉冲图案发生器。 可以向模式发生器输入开路短线，确定性抖动内容数可调，可变长短线长度。
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28.发明授权Fast detection of incorrect sampling in an oversampling clock and data recovery system 失效在过采样时钟和数据恢复系统中快速检测不正确的采样公开(公告)号：US07085970B2
公开(公告)日：2006-08-01
申请号：US10201868
申请日：2002-07-23
申请人： Gareth J. Nicholls , Alexander H. Ainscow , Jon D. Garlett , Bobak Modaress-Razavi , Vernon R. Norman , Martin L. Schmatz
发明人： Gareth J. Nicholls , Alexander H. Ainscow , Jon D. Garlett , Bobak Modaress-Razavi , Vernon R. Norman , Martin L. Schmatz
CPC分类号： H04L7/0083 , G11B20/10009 , G11B20/14 , H03L7/091 , H03L7/095 , H03L2207/14
摘要： A method, in an oversampling clock and data recovery system, for detecting that sampling is stuck taking place at a data edge, by detecting a data edge in an early or a late region relative to a good region and incrementing a stuck early or stuck late counter; and if one counter reaching a maximum, setting a condition indicating that sampling is stuck taking place at a data edge. If a data edge is detected in the good region, or in each of an early and a late region in a single data period, the stuck counters are reset to zero. The detection of which stuck counter has reached a maximum can cause the moving of a sampling clock forward or backward, ending when a data edge occurs in a good region, or in each of an early region and a late region in a single data period.
摘要翻译： 在过采样时钟和数据恢复系统中，通过检测相对于良好区域的早期或晚期区域中的数据边缘并且早期或卡滞的延迟增加来检测在数据边缘处发生采样的方法 计数器; 并且如果一个计数器达到最大值，则设置指示在数据边缘发生采样的条件。 如果在单个数据周期内的良好区域或早期和晚期区域的每个区域中检测到数据边缘，则卡住的计数器将重置为零。 哪个卡住的计数器的检测已经达到最大值可能导致采样时钟向前或向后移动，当数据沿出现在良好区域中时，或者在单个数据周期的早期区域和晚期区域中的每一个中结束。
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公开(公告)号：US5537623A
公开(公告)日：1996-07-16
申请号：US24593
申请日：1993-03-01
申请人： Dale R. Chamberlain , Joseph K. Lee , David W. Lowther , Gregory A. Mirek , Vernon R. Norman , Lee A. Sendelbach , Scott Tippens , Anthony D. Walker
发明人： Dale R. Chamberlain , Joseph K. Lee , David W. Lowther , Gregory A. Mirek , Vernon R. Norman , Lee A. Sendelbach , Scott Tippens , Anthony D. Walker
CPC分类号： H04L29/06 , H04L45/7453
摘要： A network interface card for attaching computers, work stations or the like to a Local Area Network (LAN) includes a device which indicates an address compare if selected bits in a first part of an address, in the address field of a received frame, matches bits stored in the network interface card and at least one bit of a code word stored at a particular address of an index RAM is set to a predetermined state. The particular address in the index RAM is identified by a second part of the address in the received frame. The range of address which can be recognized is further extended by a contents addressable memory (CAM) coupled to the device. The CAM makes a parallel compare between an input address and its contents and outputs a match signal if a match is found. A programmable control register is used to activate or deactivate the CAM or the device.
摘要翻译： 用于将计算机，工作站等附接到局域网（LAN）的网络接口卡包括指示地址比较的设备，如果接收帧的地址字段中的地址的第一部分中的选定位匹配 存储在网络接口卡中的位和存储在索引RAM的特定地址的代码字的至少一个位被设置为预定状态。 索引RAM中的特定地址由接收帧中地址的第二部分标识。 通过耦合到该设备的内容可寻址存储器（CAM）进一步扩展可识别的地址范围。 CAM在输入地址及其内容之间进行并行比较，如果发现匹配，则输出匹配信号。 可编程控制寄存器用于激活或停用CAM或设备。
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公开(公告)号：US5442629A
公开(公告)日：1995-08-15
申请号：US200989
申请日：1994-02-24
申请人： Joel E. Geyer , Joseph K. Lee , John M. Mullen , Vernon R. Norman , Kathleen M. Wilhelm , Kenneth T. Wilson
发明人： Joel E. Geyer , Joseph K. Lee , John M. Mullen , Vernon R. Norman , Kathleen M. Wilhelm , Kenneth T. Wilson
IPC分类号： H04L12/433 , H04L29/06 , H04J3/22
CPC分类号： H04L29/06 , H04L12/433 , H04L69/24
摘要： Dual detection paths containing speed recognition devices automatically determine the rate at which data is being transmitted on a multi-rate digital data communications network such as a token ring network. The multiple detection paths operate simultaneously with each detection path provided with a Phase Lock Loop (PLL) and a pattern recognition device. The PLL and its associated pattern recognition device are made to operate at one of the known ring speeds. The ring speed is determined by the detection path which is able to recognize a predetermined data pattern from the network.
摘要翻译： 包含速度识别装置的双重检测路径自动确定在诸如令牌环网络的多速率数字数据通信网络上传输数据的速率。 多个检测路径与设置有锁相环（PLL）和模式识别装置的每个检测路径同时操作。 PLL及其相关联的模式识别装置被制造成以已知的环速度之一工作。 环速由能够从网络识别预定数据模式的检测路径确定。
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