公开(公告)号：US06737844B2

公开(公告)日：2004-05-18

申请号：US10156583

申请日：2002-05-28

Applicant: Pradeep Trivedi ,  Sudhakar Bobba

Inventor： Pradeep Trivedi ,  Sudhakar Bobba

IPC: G05F1565

CPC classification number: G11C5/147

Abstract: A modulation circuit arranged to modulate a first voltage from a first power supply grid to produce a desired second voltage not greater than the first voltage on a second power supply grid is provided. A digital register is operatively connected to the modulation circuit to determine the desired second voltage on the second power supply grid. Furthermore, the digital register maintains a value representative of an activity level or an anticipated activity level of a circuit connected to the second power supply grid. The modulation circuit maintains the desired second voltage for the circuit connected to the second power supply grid by transferring charge between capacitances.

Abstract translation: 一种调制电路，被配置为调制来自第一电源电网的第一电压以产生不大于第二电源网格上的第一电压的期望的第二电压。 数字寄存器可操作地连接到调制电路以确定第二电源电网上的期望的第二电压。 此外，数字寄存器保持代表连接到第二电源网格的电路的活动水平或预期活动水平的值。 调制电路通过在电容之间传送电荷来维持连接到第二电源电网的电路的期望的第二电压。

公开(公告)号：US06646473B1

公开(公告)日：2003-11-11

申请号：US10170845

申请日：2002-06-13

Applicant: Pradeep Trivedi ,  Sudhakar Bobba

Inventor： Pradeep Trivedi ,  Sudhakar Bobba

IPC: H03K19096

CPC classification number: H03K19/0963 ,  H03K19/0016

Abstract: A dynamic circuit capable of operating in a normal power consumption mode and at least one reduced power consumption mode is provided. The dynamic circuit is operatively connected to a normal supply voltage and a reduced supply voltage, and is capable of operating at either the normal supply voltage and a normal frequency or at the reduced supply voltage and a reduced frequency. By using such a dynamic circuit, power consumption may be selectively controlled in order to reduce unnecessary power consumption.

Abstract translation: 提供能够以正常功耗模式和至少一个降低的功耗模式操作的动态电路。 动态电路可操作地连接到正常电源电压和降低的电源电压，并且能够在正常电源电压和正常频率或降低的电源电压和降低的频率下操作。 通过使用这样的动态电路，可以选择性地控制功率消耗，以便减少不必要的功耗。

公开(公告)号：US06861885B2

公开(公告)日：2005-03-01

申请号：US10199426

申请日：2002-07-19

Applicant: Pradeep Trivedi ,  Sudhakar Bobba ,  Claude Gauthier

Inventor： Pradeep Trivedi ,  Sudhakar Bobba ,  Claude Gauthier

IPC: H03L7/089 ,  H03L7/093 ,  H03L7/06

CPC classification number: H03L7/093 ,  H03L7/0891 ,  Y10S331/02

Abstract: A phase locked loop design uses a diode operatively connected to a loop filter capacitor to control a leakage current of the loop filter capacitor. By positioning a diode in series with the loop filter capacitor, a voltage potential across the loop filter capacitor is reduced, thereby reducing the leakage current of the loop filter capacitor. Moreover, the leakage current of the loop filter capacitor is controlled in that it cannot exceed the current through the diode. Control and reduction of the loop filter capacitor leakage current leads to more reliable and stable phase locked loop behavior.

Abstract translation: 锁相环设计使用可操作地连接到环路滤波电容器的二极管来控制环路滤波电容器的漏电流。 通过与环路滤波电容串联定位二极管，减小环路滤波电容两端的电压电位，从而减小环路滤波电容的漏电流。 此外，环路滤波电容器的漏电流被控制为不能超过二极管的电流。 控制和减少环路滤波电容器的漏电流导致更可靠和稳定的锁相环行为。

公开(公告)号：US06642756B1

公开(公告)日：2003-11-04

申请号：US10202798

申请日：2002-07-25

Applicant: Gin Yee ,  Sudhakar Bobba ,  Lynn Ooi ,  Pradeep Trivedi

Inventor： Gin Yee ,  Sudhakar Bobba ,  Lynn Ooi ,  Pradeep Trivedi

IPC: H03B1900

CPC classification number: G06F7/68 ,  H03K5/00006

Abstract: A frequency multiplier design that uses a flip-flop to output (1) a first edge on an output clock signal upon receipt of a first transition of an input clock signal and (2) a second edge on the output clock signal before receipt of a second transition of the input clock signal is provided. The frequency multiplier design uses circuitry dependent on the output clock signal to reset the flip-flop after some delay but before the second transition of the input clock signal, wherein the resetting of the flip-flop causes the flip-flop to output the second edge on the output clock signal.

Abstract translation: 一种倍增器设计，其使用触发器在接收到输入时钟信号的第一转换时输出（1）输出时钟信号上的第一边沿，以及（2）在接收到输出时钟信号之前的输出时钟信号上的第二边沿 提供输入时钟信号的第二转换。 倍频器设计使用取决于输出时钟信号的电路，在一段延迟之后但在输入时钟信号的第二次转换之前复位触发器，其中触发器的复位使触发器输出第二边沿 对输出时钟信号。

公开(公告)号：US06625791B1

公开(公告)日：2003-09-23

申请号：US10143067

申请日：2002-05-10

Applicant: Sudhakar Bobba ,  Pradeep Trivedi

Inventor： Sudhakar Bobba ,  Pradeep Trivedi

IPC: G06F945

CPC classification number: G06F17/5068

Abstract: A method and apparatus for optimizing the insertion of decoupling capacitance onto an integrated circuit is provided. Further, a sliding grid based technique for arraying decoupling capacitors into a white-space of an integrated includes sliding a bounded grid across the white-space in order to determine an optimal decap insertion for the white-space. The bounded grid is slid across the white-space in discrete steps. At each discrete step, a potential decap layout is calculated for the region of the white-space that intersects the bounded grid. After a set of potential decap layouts have been calculated for the white-space, the potential decap layout that yields optimal decap insertion is selected, and decap cells are arrayed into the area(s) of the white-space that are demarcated by the selected decap layout.

Abstract translation: 提供了一种用于优化将去耦电容插入集成电路的方法和装置。 此外，用于将去耦电容器排列到集成的白色空间中的基于滑动网格的技术包括在白色空间上滑动有界网格，以便确定白色空间的最佳切片插入。 有界网格以离散步骤滑过白色空间。 在每个离散步骤中，对于与有界网格相交的白色空间的区域计算潜在的拆分布局。 在为白色空间计算了一组潜在的拆分布局之后，选择产生最佳拆包插入的潜在的拆分布局，并将拆分单元排列到由所选择的边界划分的空白区域中 拆分布局。

公开(公告)号：US06570423B1

公开(公告)日：2003-05-27

申请号：US10230596

申请日：2002-08-29

Applicant: Pradeep R. Trivedi ,  Claude R. Gauthier ,  Sudhakar Bobba

Inventor： Pradeep R. Trivedi ,  Claude R. Gauthier ,  Sudhakar Bobba

IPC: H03L706

CPC classification number: H03L7/0893 ,  H03L7/18

Abstract: A method and apparatus for post-fabrication adjustment of a phased locked loop leakage current is provided. The adjustment system includes a programmable current source that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the phase locked loop. The programmable current source includes at least one current source and switch to adjust the leakage current offset circuit. The programmable current source is selectively adjusted by a combinational logic circuit. Such control of the leakage current in the phased locked loop allows a designer to achieve a desired phase locked loop operating characteristic after fabrication of the adjustable phase locked loop.

Abstract translation: 提供了一种用于相位锁定环路漏电流的制造后调整的方法和装置。 调节系统包括一个可编程电流源，调节漏电流补偿电路以补偿电容器的漏电流。 电容器连接到锁相环的控制电压。 可编程电流源包括至少一个电流源和用于调整漏电流补偿电路的开关。 可编程电流源由组合逻辑电路选择性地调节。 对相位锁定环中的漏电流的这种控制允许设计者在制造可调锁相环之后实现期望的锁相环工作特性。

公开(公告)号：US06570422B1

公开(公告)日：2003-05-27

申请号：US10199421

申请日：2002-07-19

Applicant: Pradeep Trivedi ,  Sudhakar Bobba ,  Claude R. Gauthier

Inventor： Pradeep Trivedi ,  Sudhakar Bobba ,  Claude R. Gauthier

IPC: H03L706

CPC classification number: H03L7/18 ,  H03L7/0891

Abstract: A phase locked loop design that uses a switch operatively connected to a loop filter capacitor to control a leakage current of the loop filter capacitor is provided. By positioning a switch in series with the loop filter capacitor, the leakage current of the loop filter capacitor may be controlled by switching the switch ‘on’ when a charge pump of the phase locked loop is ‘on’ and switching the switch ‘off’ when the charge pump is ‘off,’ thereby cumulatively reducing the leakage current of the loop filter capacitor throughput the operation of the phase locked loop. Control and reduction of the loop filter capacitor leakage current leads to more reliable and stable phase locked loop behavior.

Abstract translation: 提供了一种锁相环设计，其使用可操作地连接到环路滤波电容器的开关来控制环路滤波电容器的漏电流。 通过将开关与环路滤波电容器串联定位，可以通过在锁相环的电荷泵“开”时切换开关“开”来控制环路滤波电容器的漏电流，并将开关“断开” 当电荷泵“关闭”时，累积降低了环路滤波电容器的泄漏电流，达到了锁相环的运行。 控制和减少环路滤波电容器的漏电流导致更可靠和稳定的锁相环行为。

公开(公告)号：US20110291630A1

公开(公告)日：2011-12-01

申请号：US12787135

申请日：2010-05-25

Applicant: Georgios Konstadinidis ,  Sudhakar Bobba ,  David Greenhill

Inventor： Georgios Konstadinidis ,  Sudhakar Bobba ,  David Greenhill

IPC: G05F1/10

CPC classification number: H02M3/157 ,  H02M2001/0025

Abstract: Disclosed is a digital voltage regulator system and method for mitigating voltage droop in an integrated circuit. If an unacceptable voltage droop is detected, the digital voltage regulator may take action to allow the power supply voltage to recover. A digital voltage regulator in accordance with embodiments discussed herein detects voltage droop by comparing a power supply voltage measurement with a threshold voltage. The threshold voltage may be calibrated based on power supply voltage measurements taken while the integrated circuit is operating.

Abstract translation: 公开了用于减轻集成电路中的电压下降的数字电压调节器系统和方法。 如果检测到不可接受的电压下降，则数字电压调节器可采取动作以允许电源电压恢复。 根据本文讨论的实施例的数字电压调节器通过将电源电压测量与阈值电压进行比较来检测电压下降。 阈值电压可以基于集成电路运行时所采用的电源电压测量来校准。

公开(公告)号：US20100229021A1

公开(公告)日：2010-09-09

申请号：US12399736

申请日：2009-03-06

Applicant: Georgios K. Konstadinidis ,  Sudhakar Bobba

Inventor： Georgios K. Konstadinidis ,  Sudhakar Bobba

IPC: G06F1/08 ,  G06F1/28

CPC classification number: G06F1/305 ,  G06F1/08 ,  G06F1/3203

Abstract: A voltage droop monitoring and correcting circuit for a microprocessor includes: a monitor circuit configured to monitor voltage droops of the microprocessor and perform a temporary clock-skipping technique to compensate for the voltage droops. A method for monitoring and correcting voltage droops of a microprocessor includes: monitoring voltage droops of the microprocessor; and performing a temporary clock-skipping technique to compensate for the voltage droops. A computer system includes memory; a processor operatively connected to the memory; and computer-readable instructions stored in the memory for causing the processor to: monitor voltage droops of the microprocessor; and perform a temporary clock-skipping technique to compensate for the voltage droops.

Abstract translation: 用于微处理器的电压下降监视和校正电路包括：监视器电路，被配置为监视微处理器的电压下降并执行暂时的跳时技术以补偿电压下降。 用于监视和校正微处理器的电压下降的方法包括：监视微处理器的电压下降; 并执行临时跳时技术以补偿电压下降。 计算机系统包括存储器; 可操作地连接到存储器的处理器; 以及存储在存储器中的计算机可读指令，用于使处理器：监视微处理器的电压下降; 并执行临时的时钟跳跃技术来补偿电压下降。

公开(公告)号：US06646472B1

公开(公告)日：2003-11-11

申请号：US10156249

申请日：2002-05-28

Applicant: Pradeep Trivedi ,  Sudhakar Bobba

Inventor： Pradeep Trivedi ,  Sudhakar Bobba

IPC: H03K1900

CPC classification number: G06F1/10 ,  G06F1/3203

Abstract: A technique for reducing the power consumed by a clock driver circuit involves selecting between a first power supply path and a second power supply path in response to a power reduction signal. A driver circuit drives an output clock signal from the selected one of the first power supply path and the second power supply path. By reducing the voltage on one of the first power supply path and the second power supply path, the power consumed by the clock driver circuit may be selectively reduced.

Abstract translation: 用于减少时钟驱动器电路消耗的功率的技术包括响应于功率降低信号在第一电源路径和第二电源路径之间进行选择。 驱动电路驱动来自第一电源路径和第二电源路径中选择的一个的输出时钟信号。 通过降低第一电源路径和第二电源路径中的一个电压，可以选择性地减少由时钟驱动器电路消耗的功率。