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    Frequency multiplier design
    1.
    发明授权
    Frequency multiplier design 有权
    倍频器设计

    公开(公告)号：US06642756B1

    公开(公告)日：2003-11-04

    申请号：US10202798

    申请日：2002-07-25

    申请人： Gin Yee ,  Sudhakar Bobba ,  Lynn Ooi ,  Pradeep Trivedi

    发明人： Gin Yee ,  Sudhakar Bobba ,  Lynn Ooi ,  Pradeep Trivedi

    IPC分类号： H03B1900

    CPC分类号： G06F7/68 ,  H03K5/00006

    摘要： A frequency multiplier design that uses a flip-flop to output (1) a first edge on an output clock signal upon receipt of a first transition of an input clock signal and (2) a second edge on the output clock signal before receipt of a second transition of the input clock signal is provided. The frequency multiplier design uses circuitry dependent on the output clock signal to reset the flip-flop after some delay but before the second transition of the input clock signal, wherein the resetting of the flip-flop causes the flip-flop to output the second edge on the output clock signal.

    摘要翻译： 一种倍增器设计，其使用触发器在接收到输入时钟信号的第一转换时输出（1）输出时钟信号上的第一边沿，以及（2）在接收到输出时钟信号之前的输出时钟信号上的第二边沿 提供输入时钟信号的第二转换。 倍频器设计使用取决于输出时钟信号的电路，在一段延迟之后但在输入时钟信号的第二次转换之前复位触发器，其中触发器的复位使触发器输出第二边沿 对输出时钟信号。

    Duty cycle corrector
    2.
    发明授权
    Duty cycle corrector 有权
    占空比校正器

    公开(公告)号：US06882196B2

    公开(公告)日：2005-04-19

    申请号：US10198453

    申请日：2002-07-18

    申请人： Gin Yee ,  Sudhakar Bobba ,  Claude Gauthier ,  Dean Liu ,  Lynn Ooi ,  Pradeep Trivedi

    发明人： Gin Yee ,  Sudhakar Bobba ,  Claude Gauthier ,  Dean Liu ,  Lynn Ooi ,  Pradeep Trivedi

    IPC分类号： H03K3/017 ,  H03K5/00 ,  H03K5/156

    CPC分类号： H03K5/1565 ,  H03K2005/00045

    摘要： A device that uses an input clock signal to generate an output clock signal with a desired frequency is provided. The device uses a voltage controlled delay element that outputs a reset signal to a flip-flop dependent on a bias signal and the input clock signal. When triggered, the flip-flop outputs a transition on the output clock signal, which, in turn, serves as an input to a duty cycle corrector that generates the bias signal dependent on the configuration of the duty cycle corrector. The duty cycle corrector may be configured to generate the bias signal so as to be able to operatively control the duty cycle of the output clock signal.

    摘要翻译： 提供了使用输入时钟信号来产生具有期望频率的输出时钟信号的装置。 该器件使用电压控制延迟元件，其根据偏置信号和输入时钟信号将触发器输出复位信号。 当触发时，触发器输出输出时钟信号的转变，输出时钟信号又作为占空比校正器的输入，占空比校正器根据占空比校正器的配置产生偏置信号。 占空比校正器可以被配置为产生偏置信号，以便能够可操作地控制输出时钟信号的占空比。

    Accuracy of timing analysis using region-based voltage drop budgets
    3.
    发明授权
    Accuracy of timing analysis using region-based voltage drop budgets 有权
    使用基于区域的电压降预算的时序分析的准确性

    公开(公告)号：US06971079B2

    公开(公告)日：2005-11-29

    申请号：US10245972

    申请日：2002-09-18

    申请人： Gin Yee ,  Pradeep Trivedi ,  Sudhakar Bobba

    发明人： Gin Yee ,  Pradeep Trivedi ,  Sudhakar Bobba

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5031

    摘要： A method and apparatus for improving the timing accuracy of an integrated circuit through region-based voltage drop budgets is provided. Further, a method for performing timing analysis on an integrated circuit partitioned into voltage drop regions is provided. During the timing analysis, a set of logic paths segments in each voltage drop region is tested to ensure that the integrated circuit meets a set of predefined timing requirements. Logic path segments that reside in different voltage drop regions are tested using a supply voltage inputted by the respective voltage drop region.

    摘要翻译： 提供了一种通过基于区域的电压降预算来提高集成电路的定时精度的方法和装置。 此外，提供了一种用于对分压成电压降区域的集成电路进行定时分析的方法。 在定时分析期间，测试每个压降区域中的一组逻辑路径段，以确保集成电路满足一组预定义的时序要求。 使用由各个电压降区域输入的电源电压来测试驻留在不同电压降区域中的逻辑路径段。

    Region-based voltage drop budgets for low-power design
    4.
    发明授权
    Region-based voltage drop budgets for low-power design 有权
    用于低功率设计的基于区域的电压降预算

    公开(公告)号：US06976235B2

    公开(公告)日：2005-12-13

    申请号：US10246089

    申请日：2002-09-18

    申请人： Sudhakar Bobba ,  Gin Yee ,  Pradeep Trivedi

    发明人： Sudhakar Bobba ,  Gin Yee ,  Pradeep Trivedi

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5036 ,  G06F2217/78

    摘要： A method and apparatus for assigning a set of region-based voltage drop budgets to an integrated circuit is provided. Further, a method for partitioning an integrated circuit into optimal voltage drop regions includes analyzing the integrated circuit for worst-case voltage drop data. The worst-case voltage drop data is used to partition the integrated circuit into a set of voltage drop regions, wherein each voltage drop region is assigned a region-based voltage drop budget. The region-based voltage drop budget assigned to a particular voltage drop region is based on a worst-case voltage drop experienced by that voltage drop region.

    摘要翻译： 提供了一种用于将一组基于区域的电压降预算分配给集成电路的方法和装置。 此外，用于将集成电路划分成最佳压降区域的方法包括分析集成电路以获得最坏情况的电压降数据。 最坏情况的电压降数据用于将集成电路分成一组电压降区域，其中每个电压降区域被分配有基于区域的电压降预算。 分配给特定电压降区域的基于区域的电压降预算是基于该压降区域经历的最坏情况的电压降。

    Transmission gate based signal transition accelerator
    5.
    发明授权
    Transmission gate based signal transition accelerator 有权
    基于传输门限的信号转换加速器

    公开(公告)号：US06784689B2

    公开(公告)日：2004-08-31

    申请号：US10068671

    申请日：2002-02-06

    申请人： Sudhakar Bobba ,  Pradeep Trivedi

    发明人： Sudhakar Bobba ,  Pradeep Trivedi

    IPC分类号： H03K1716

    CPC分类号： H04L25/242 ,  H03K5/12 ,  H03K19/01707

    摘要： A negative impedance device that accelerates signal transitions on a signal is provided. The negative impedance device is highly responsive to high to low and low to high transitions on the signal, and when one of these types of transitions begins to occur on the signal, the negative impedance device senses the transition and quickly drives the signal to the intended value before a point in time when the signal would have reached the intended value had the negative impedance device not been used. Further, a signal transition accelerator design that reduces signal rise and fall times is provided. Further, a method for accelerating a signal transition is provided.

    摘要翻译： 提供加速信号上的信号转换的负阻抗器件。 负阻抗器件对信号的高到低和低到高的转变都是高度响应的，并且当这些类型的转换之一在信号上开始发生时，负阻抗器件感测到转换并且迅速地将信号驱动到预期 在信号将达到预期值的时间点之前的值未被使用的负阻抗器件。 此外，提供了降低信号上升和下降时间的信号转换加速器设计。 此外，提供了一种加速信号转换的方法。

    Dynamic modulation of on-chip supply voltage for low-power design
    6.
    发明授权
    Dynamic modulation of on-chip supply voltage for low-power design 有权
    低功耗设计的片上电源动态调制

    公开(公告)号：US06737844B2

    公开(公告)日：2004-05-18

    申请号：US10156583

    申请日：2002-05-28

    申请人： Pradeep Trivedi ,  Sudhakar Bobba

    发明人： Pradeep Trivedi ,  Sudhakar Bobba

    IPC分类号： G05F1565

    CPC分类号： G11C5/147

    摘要： A modulation circuit arranged to modulate a first voltage from a first power supply grid to produce a desired second voltage not greater than the first voltage on a second power supply grid is provided. A digital register is operatively connected to the modulation circuit to determine the desired second voltage on the second power supply grid. Furthermore, the digital register maintains a value representative of an activity level or an anticipated activity level of a circuit connected to the second power supply grid. The modulation circuit maintains the desired second voltage for the circuit connected to the second power supply grid by transferring charge between capacitances.

    摘要翻译： 一种调制电路，被配置为调制来自第一电源电网的第一电压以产生不大于第二电源网格上的第一电压的期望的第二电压。 数字寄存器可操作地连接到调制电路以确定第二电源电网上的期望的第二电压。 此外，数字寄存器保持代表连接到第二电源网格的电路的活动水平或预期活动水平的值。 调制电路通过在电容之间传送电荷来维持连接到第二电源电网的电路的期望的第二电压。

    Multiple supply voltage dynamic logic
    7.
    发明授权
    Multiple supply voltage dynamic logic 有权
    多电源电压动态逻辑

    公开(公告)号：US06646473B1

    公开(公告)日：2003-11-11

    申请号：US10170845

    申请日：2002-06-13

    申请人： Pradeep Trivedi ,  Sudhakar Bobba

    发明人： Pradeep Trivedi ,  Sudhakar Bobba

    IPC分类号： H03K19096

    CPC分类号： H03K19/0963 ,  H03K19/0016

    摘要： A dynamic circuit capable of operating in a normal power consumption mode and at least one reduced power consumption mode is provided. The dynamic circuit is operatively connected to a normal supply voltage and a reduced supply voltage, and is capable of operating at either the normal supply voltage and a normal frequency or at the reduced supply voltage and a reduced frequency. By using such a dynamic circuit, power consumption may be selectively controlled in order to reduce unnecessary power consumption.

    摘要翻译： 提供能够以正常功耗模式和至少一个降低的功耗模式操作的动态电路。 动态电路可操作地连接到正常电源电压和降低的电源电压，并且能够在正常电源电压和正常频率或降低的电源电压和降低的频率下操作。 通过使用这样的动态电路，可以选择性地控制功率消耗，以便减少不必要的功耗。

    Phase locked loop design with diode for loop filter capacitance leakage current control
    9.
    发明授权
    Phase locked loop design with diode for loop filter capacitance leakage current control 有权
    具有二极管的锁相环设计，用于环路滤波器电容漏电流控制

    公开(公告)号：US06861885B2

    公开(公告)日：2005-03-01

    申请号：US10199426

    申请日：2002-07-19

    申请人： Pradeep Trivedi ,  Sudhakar Bobba ,  Claude Gauthier

    发明人： Pradeep Trivedi ,  Sudhakar Bobba ,  Claude Gauthier

    IPC分类号： H03L7/089 ,  H03L7/093 ,  H03L7/06

    CPC分类号： H03L7/093 ,  H03L7/0891 ,  Y10S331/02

    摘要： A phase locked loop design uses a diode operatively connected to a loop filter capacitor to control a leakage current of the loop filter capacitor. By positioning a diode in series with the loop filter capacitor, a voltage potential across the loop filter capacitor is reduced, thereby reducing the leakage current of the loop filter capacitor. Moreover, the leakage current of the loop filter capacitor is controlled in that it cannot exceed the current through the diode. Control and reduction of the loop filter capacitor leakage current leads to more reliable and stable phase locked loop behavior.

    摘要翻译： 锁相环设计使用可操作地连接到环路滤波电容器的二极管来控制环路滤波电容器的漏电流。 通过与环路滤波电容串联定位二极管，减小环路滤波电容两端的电压电位，从而减小环路滤波电容的漏电流。 此外，环路滤波电容器的漏电流被控制为不能超过二极管的电流。 控制和减少环路滤波电容器的漏电流导致更可靠和稳定的锁相环行为。