Timing analysis apparatus and method for semiconductor integrated circuit in consideration of power supply and ground noises
    21.
    发明授权
    Timing analysis apparatus and method for semiconductor integrated circuit in consideration of power supply and ground noises 失效
    考虑到电源和地面噪声的半导体集成电路的时序分析装置和方法

    公开(公告)号:US08020130B2

    公开(公告)日:2011-09-13

    申请号:US12254295

    申请日:2008-10-20

    申请人: Makoto Nagata

    发明人: Makoto Nagata

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5031

    摘要: In a timing analysis apparatus for use in a semiconductor integrated circuit, which analyzes operation timing of a semiconductor integrated circuit having a logic gate circuit including a plurality of logic gates, a controller detects at least one of a power supply voltage and a ground voltage of a power supply, decomposes the noise waveform into frequency components, classifies the frequency components into low-frequency components lower than a predetermined threshold frequency and high-frequency components higher than the threshold frequency, calculates a static delay time of each of the logic gates due to the low-frequency components, calculates a dynamic delay time of each of the logic gates due to the high-frequency components, and determines a delay time of each of the logic gates by synthesizing the calculated respective delay times.

    摘要翻译: 在用于分析具有包括多个逻辑门的逻辑门电路的半导体集成电路的操作定时的半导体集成电路中的定时分析装置中,控制器检测电源电压和接地电压中的至少一个 电源将噪声波形分解为频率分量,将频率分量分类为低于预定阈值频率的低频分量和高于阈值频率的高频分量,计算每个逻辑门的静态延迟时间 对于低频分量,由于高频分量而计算每个逻辑门的动态延迟时间,并且通过合成所计算的各个延迟时间来确定每个逻辑门的延迟时间。

    On-chip signal waveform measurement apparatus for measuring signal waveforms at detection points on IC chip

    公开(公告)号:US20060197697A1

    公开(公告)日:2006-09-07

    申请号:US11366835

    申请日:2006-03-03

    申请人: Makoto Nagata

    发明人: Makoto Nagata

    IPC分类号: G01S13/00

    CPC分类号: G01R31/2884 G01R31/31924

    摘要: An on-chip signal waveform measurement apparatus mounted on an IC chip measures signal waveforms at detection points on the IC chip. A reference voltage generator successively generates reference voltages different from each other based on a predetermined timing signal, and Signal probing front-end circuits are mounted to correspond to the detection points, respectively, and each buffer-amplifies a voltage at each detection point, compares the buffer-amplified voltage with each reference voltage, and digitizes a comparison result into a binary digital output signal. A multiplexer time-division-multiplexes the binary digital output signals from the signal probing front-end circuits. A data processing unit calculates a judgment output probability for a detected voltage at each detection point detected by the respective signal probing front-end circuits, by counting a number of times of a predetermined binary value of the multiplexed binary digital output signal.

    Film, laminated film and laminated structure
    24.
    发明授权
    Film, laminated film and laminated structure 失效
    膜,层压膜和层压结构

    公开(公告)号:US06284355B1

    公开(公告)日:2001-09-04

    申请号:US09312707

    申请日:1999-05-17

    IPC分类号: B32B2732

    摘要: There are provided: a film(F) obtained by heat-aging a film containing a specific propylene resin; a laminated film(LF-1) having (i)a layer containing a specific propylene resin, and (ii)a layer containing a specific propylene block copolymer; a laminated film(LF-2) obtained by heat-aging the laminated film(LF-1); a laminated structure(LS-1) having (a)a substrate containing an olefinic resin, and (b)the film(F); a laminated structure(LS-2) having (a)a substrate containing an olefinic resin, and (b)the laminated film(LF-1); a laminated structure(LS-3) obtained by heat-aging said laminated structure(LS-2); a laminated structure(LS-4) having (a)a substrate containing an olefinic resin, and (b)a laminated film(LF-2); and a laminated structure(LS-5) having (a)a substrate containing an olefinic resin, and (b)a film containing a specific propylene resin.

    摘要翻译: 提供:通过将含有特定丙烯类树脂的膜热老化获得的膜(F);具有(i)含有特定丙烯类树脂的层的层压膜(LF-1),和(ii)含有 特别是丙烯嵌段共聚物,通过将层叠膜(LF-1)进行热老化而得到的层压膜(LF-2);具有(a)含有烯烃树脂的基材的层压结构体(LS-1),(b) 膜(F);具有(a)含有烯烃树脂的基材的层叠结构体(LS-2),(b)层叠膜(LF-1),通过热处理得到的层叠结构体(LS-3) 老化所述层压结构(LS-2);层压结构(LS-4),其具有(a)含有烯烃树脂的基材和(b)层压膜(LF-2); 和具有(a)含有烯烃树脂的基材的层叠结构体(LS-5),(b)含有特定丙烯类树脂的膜。

    Projection type display unit
    25.
    发明申请
    Projection type display unit 失效
    投影型显示单元

    公开(公告)号:US20070070298A1

    公开(公告)日:2007-03-29

    申请号:US11440004

    申请日:2006-05-25

    IPC分类号: G03B21/18 G03B21/26

    CPC分类号: G03B21/18

    摘要: An armor cabinet of a projection type display unit includes a base cabinet on which main component parts are mounted, and a top cover made from sheet metal which is mounted so as to cover the base cabinet, wherein a rear face portion composed of the top cover is formed in the shape of a curved surface being laid-down U-shaped in side view. At the time of carrying the projection type display unit, the rear face portion in the U-shaped curved surface shape is just fitted to the palm on an ergonomic basis, and the grip can range to the fingertips, so that the rear face portion can be gripped assuredly and securely even with one hand. On the back side of the top cover, bosses are integrally formed by use of a resin which is a different material from the sheet metal of the top cover, and the base cabinet and the top cover are fixed by fastening screws to the bosses from the base cabinet side.

    摘要翻译: 投影式显示单元的装甲柜包括:安装有主要部件的基座机壳和由金属板制成的覆盖基座的顶盖,其中由顶盖构成的后表面部分 形成为侧视图中呈U字形的弯曲表面的形状。 在携带投影型显示单元时,U形曲面形状的后表面部分以人体工程学原理恰好装配到手掌上,并且把手可以在指尖的范围内,使得背面部分可以 一手抓住,牢固牢固。 在顶盖的后侧,通过使用与顶盖的金属板不同的材料的树脂将凸台一体地形成,并且底座和顶盖通过紧固螺钉固定到凸台上 底柜侧。

    Method and apparatus for analyzing a source current waveform in a semiconductor integrated circuit
    26.
    发明授权
    Method and apparatus for analyzing a source current waveform in a semiconductor integrated circuit 失效
    用于分析半导体集成电路中的源电流波形的方法和装置

    公开(公告)号:US07039536B2

    公开(公告)日:2006-05-02

    申请号:US09977994

    申请日:2001-10-17

    IPC分类号: G06F17/00

    CPC分类号: G06F17/5036 G01R31/3004

    摘要: The invention provides a method of analyzing a source current at a higher speed and an enhanced accuracy in a semiconductor integrated circuit including a digital circuit. The method to analyze a waveform of the source current, with consideration of re-distribution of charges throughout the digital circuit in the semiconductor integrated circuit, expressing the digital circuit with series of parasitic capacitors ΣCch, ↑ (nT) and ΣCch, ↓ (nT) to be charged and connected between the source and the ground lines. The capacitor series are calculated in time series based on the distribution of switching operations of the logic gates included in the digital circuit. An analysis model for determining the waveform of the source current in the digital circuit is obtained by connecting the parasitic capacitor series with a couple of respective parasitic impedances Zd and Zg of the source line and the ground line.

    摘要翻译: 本发明提供了一种在包括数字电路的半导体集成电路中以更高的速度和更高的精度来分析源电流的方法。 考虑到在半导体集成电路中的整个数字电路中的电荷的再分配,分析源极电流的波形的方法,表示具有一系列寄生电容器的数字电路SigmaC< ch> nT)和SigmaC ch,↓(nT),以在源极和地线之间被充电和连接。 基于包括在数字电路中的逻辑门的开关操作的分布,以时间序列计算电容器系列。 用于确定数字电路中的源电流的波形的分析模型通过将寄生电容器系列与一对相应的寄生阻抗Z SUB和Z SUB连接在一起而获得 源极线和地线。

    Low switching noise logic circuit
    28.
    发明授权
    Low switching noise logic circuit 失效
    低开关噪声逻辑电路

    公开(公告)号:US6144217A

    公开(公告)日:2000-11-07

    申请号:US348584

    申请日:1999-07-07

    CPC分类号: H03K19/00361

    摘要: An analog-digital hybrid IC device for reducing cross-talk adds an electrostatic capacitance element to the power supply side and/or the ground side of a CMOS logic circuit forming the digital circuit part, connects a resistance between the electrostatic capacitance element and the terminal to which the electrostatic capacitance element was added, and buffers charging and discharging when the logic elements switch on and off to reduce noise produced by current peaks.

    摘要翻译: 用于减少串扰的模拟数字混合IC装置在形成数字电路部分的CMOS逻辑电路的电源侧和/或接地侧增加静电电容元件,连接静电电容元件与端子之间的电阻 添加静电电容元件,并且当逻辑元件接通和断开时缓冲器充电和放电,以减少由电流峰值产生的噪声。

    Apparatus for processing two-dimensional information
    29.
    发明授权
    Apparatus for processing two-dimensional information 失效
    二维信息处理装置

    公开(公告)号:US6088490A

    公开(公告)日:2000-07-11

    申请号:US47378

    申请日:1998-03-25

    CPC分类号: G06T1/20

    摘要: A two-dimensional information processing apparatus comprises a plurality of unit cell circuits arranged in a tow-dimensional matrix and each including a detector for detecting information as predetermined part of two-dimensional information, a storage circuit for storing the information detected by the detector, and a signal processing circuit for generating a pulse width modulation signal which has a pulse width corresponding to the information detected or stored, a plurality of address lines extending in a direction of columns of the matrix, and each connected to those unit cell circuits which are included in a corresponding one of the columns, a plurality of bus lines extending in a direction of rows of the matrix, and each connected to those unit cell circuits which are included in a corresponding one of the rows, means for selecting at least one of the address lines and supplying, through the selected address line, a control signal for generating a pulse width modulation signal to those unit cell circuits which are included in the selected bus line, and means for selecting at least one of the bus lines and reading, through the selected bus line, at least one pulse width modulation signal. The control signal includes a ramp signal, and the pulse modulation signal rises when the voltage of the ramp signal starts to increase, and falls when the voltage of the ramp signal is identical to a voltage determined on the basis of the information detected by the detector.

    摘要翻译: 一种二维信息处理装置,包括:多维单位电路,以多维矩阵的形式排列,每一个都包含检测信息作为二维信息的预定部分的检测器;存储检测器检测出的信息的存储电路; 以及信号处理电路,用于产生具有与检测或存储的信息相对应的脉冲宽度的脉宽调制信号,沿矩阵列的方向延伸的多个地址线,并且每个连接到那些单元电路 包括在对应的一列中,沿矩阵行的方向延伸的多个总线,并且每个连接到包括在相应的一行中的那些单元电路,用于选择以下各项中的至少一个的装置: 地址线,并通过所选地址线提供用于产生脉宽调制信号的控制信号 包括在所选择的总线中的那些单元电路,以及用于选择至少一个总线并通过所选择的总线读取至少一个脉冲宽度调制信号的装置。 控制信号包括斜坡信号,并且当斜坡信号的电压开始增加时,脉冲调制信号上升,当斜坡信号的电压与基于由检测器检测到的信息确定的电压相同时,脉冲调制信号下降 。

    Impact energy absorptive structures
    30.
    发明授权
    Impact energy absorptive structures 失效
    冲击能量吸收结构

    公开(公告)号:US5925435A

    公开(公告)日:1999-07-20

    申请号:US538849

    申请日:1995-10-04

    IPC分类号: F16F7/12

    摘要: An impact energy absorptive structure is made of usual plastic materials suitable for molding processing, and is designed to suit different degrees of impact loading anticipated in various applications. The impact energy absorptive structure is composed of a base member 11 and protruding rib members including long and short members, in which the proportion of the cross sectional area of the long rib members is between 0.3 to 0.8 of the total cross sectional area of the rib members. Other design modifications can be made readily to customize the impact resistance of the impact energy absorptive structures.

    摘要翻译: 冲击能量吸收结构由适用于模塑加工的通常的塑料材料制成,并且被设计成适合各种应用中预期的不同程度的冲击载荷。 冲击能量吸收结构由基部构件11和包括长构件和短构件的突出肋构件组成,其中长肋构件的横截面积的比例在肋的总横截面面积的0.3至0.8之间 会员 可以容易地进行其他设计修改以定制冲击能量吸收结构的耐冲击性。